FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [NFCI][DebugInfo] Corrected a comment. (details)
  2. [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets (details)
  3. [LLDB] Disable MSVC warning C4190: (details)
  4. [Object/ELF] - Refine the error reported when section's offset + size (details)
  5. Precommit tests for D70673 (details)
  6. [DDG] Data Dependence Graph - Topological Sort (Memory Leak Fix) (details)
  7. [DebugInfo] Make DebugVariable class available in DebugInfoMetadata (details)
  8. [libomptarget] Build a minimal deviceRTL for amdgcn (details)
Commit 8dd17a13b04f00c41bc72fdb12a552f2df26e516 by SourabhSingh.Tomar
[NFCI][DebugInfo] Corrected a comment.
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Commit 8bf31e28d7b6eb5743bda82fc5f8a98152b50e57 by sander.desmalen
[Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets
This patch adds intrinsics for SVE gather loads for which the offsets
are 32-bits wide and are:
* unscaled
* @llvm.aarch64.sve.ld1.gather.sxtw
* @llvm.aarch64.sve.ld1.gather.uxtw
* scaled (offsets become indices)
* @llvm.arch64.sve.ld1.gather.sxtw.index
* @llvm.arch64.sve.ld1.gather.uxtw.index The offsets are either zero
(uxtw) or sign (sxtw) extended to 64 bits.
These intrinsics map 1-1 to the corresponding SVE instructions (examples
for half-words):
* unscaled
* ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
* ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
* scaled
* ld1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]
* ld1h { z0.s }, p0/z, [x0, z0.s, uxtw #1]
Committed on behalf of Andrzej Warzynski (andwar)
Reviewers: sdesmalen, kmclaughlin, eli.friedman, rengolin, rovka,
huntergr, dancgr, mgudim, efriedma
Reviewed By: sdesmalen
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70782
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-unscaled-offsets.ll
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-scaled-offsets.ll
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit 1cc0ba4cbdc54200e1b3c65e83e51a5368a819ea by alexandre.ganea
[LLDB] Disable MSVC warning C4190:
'LLDBSwigPythonBreakpointCallbackFunction' has C-linkage specified, but
returns UDT 'llvm::Expected<bool>' which is incompatible with C
Differential Revision: https://reviews.llvm.org/D70830
The file was modifiedlldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
Commit d7ecc0256ebda38e4c746a1ed0faeb3005410d93 by grimar
[Object/ELF] - Refine the error reported when section's offset + size
overruns the file buffer.
This is a follow-up requested in comments for D70826.
It changes the message from
"section X has a sh_offset (Y) + sh_size (Z) that cannot be represented"
to
"section X has a sh_offset (Y) + sh_size (Z) that is greater than the
file size (0xABC)"
when section's sh_offset + sh_size overruns a file buffer.
Differential revision: https://reviews.llvm.org/D70893
The file was modifiedllvm/test/tools/llvm-readobj/elf-verdef-invalid.test
The file was modifiedllvm/test/tools/llvm-readobj/elf-verneed-invalid.test
The file was modifiedllvm/include/llvm/Object/ELF.h
The file was modifiedllvm/test/Object/invalid.test
Commit 970d9719ea0d15795694d7686d4d8eb524bba379 by Sanne.Wouda
Precommit tests for D70673
The file was modifiedllvm/test/CodeGen/AArch64/neon-mla-mls.ll
The file was addedllvm/test/CodeGen/AArch64/overeager_mla_fusing.ll
Commit 2dd82a1c04961cac05966f29d22a2b4b42b01b69 by bmahjour
[DDG] Data Dependence Graph - Topological Sort (Memory Leak Fix)
Summary: This fixes the memory leak in
bec37c3fc766a7b97f8c52c181c325fd47b75259 and re-delivers the reverted
patch. In this patch the DDG DAG is sorted topologically to put the
nodes in the graph in the order that would satisfy all dependencies.
This helps transformations that would like to generate code based on the
DDG. Since the DDG is a DAG a reverse-post-order traversal would give us
the topological ordering. This patch also sorts the basic blocks passed
to the builder based on program order to ensure that the dependencies
are computed in the correct direction.
Authored By: bmahjour
Reviewer: Meinersbur, fhahn, myhsu, xtian, dmgreen, kbarton, jdoerfert
Reviewed By: Meinersbur
Subscribers: ychen, arphaman, simoll, a.elovikov, mgorny, hiraditya,
jfb, wuzish, llvm-commits, jsji, Whitney, etiotto, ppc-slack
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70609
The file was modifiedllvm/test/Analysis/DDG/basic-a.ll
The file was modifiedllvm/include/llvm/Analysis/DDG.h
The file was modifiedllvm/test/Analysis/DDG/root-node.ll
The file was modifiedllvm/lib/Analysis/DependenceGraphBuilder.cpp
The file was modifiedllvm/lib/Analysis/DDG.cpp
The file was modifiedllvm/test/Analysis/DDG/basic-loopnest.ll
The file was modifiedllvm/include/llvm/Analysis/DependenceGraphBuilder.h
The file was modifiedllvm/test/Analysis/DDG/basic-b.ll
Commit 269a9afe25cb0ab7a7c0c62b9d95975ffc653530 by stozer
[DebugInfo] Make DebugVariable class available in DebugInfoMetadata
The DebugVariable class is a class declared in LiveDebugValues.cpp which
is used to uniquely identify a single variable, using its source
variable, inline location, and fragment info to do so. This patch moves
this class into DebugInfoMetadata.h, making it available in a much
broader scope.
The file was modifiedllvm/lib/CodeGen/LiveDebugValues.cpp
The file was modifiedllvm/include/llvm/IR/DebugInfoMetadata.h
The file was modifiedllvm/lib/IR/DebugInfoMetadata.cpp
The file was modifiedllvm/unittests/IR/MetadataTest.cpp
Commit 877ffa716fba52251a7454ffd3727d025b617a1f by jonathanchesterfield
[libomptarget] Build a minimal deviceRTL for amdgcn
Summary:
[libomptarget] Build a minimal deviceRTL for amdgcn
The CMakeLists.txt file is functionally identical to the one used in the
aomp fork. Whitespace changes were made based on nvptx/CMakeLists.txt,
plus the copyright notice updated to match (Greg was the original author
so would like his sign off on that here).
This change will build a small subset of the deviceRTL if an appropriate
toolchain is available, e.g. a local install of rocm. Support.h is moved
from nvptx as a dependency of debug.h.
Reviewers: jdoerfert, ABataev, grokos, ronlieb, gregrodgers
Reviewed By: jdoerfert
Subscribers: jfb, Hahnfeld, jvesely, mgorny, openmp-commits
Tags: #openmp
Differential Revision: https://reviews.llvm.org/D70414
The file was addedopenmp/libomptarget/deviceRTLs/common/support.h
The file was addedopenmp/libomptarget/deviceRTLs/amdgcn/src/device_environment.h
The file was removedopenmp/libomptarget/deviceRTLs/nvptx/src/support.h
The file was addedopenmp/libomptarget/deviceRTLs/amdgcn/CMakeLists.txt
The file was modifiedopenmp/libomptarget/deviceRTLs/CMakeLists.txt
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/src/target_impl.h