SuccessChanges

Summary

  1. Revert "[X86][SSE] Shuffle combine blends to OR(X,Y) if the relevant elements are known zero." (details)
  2. [WebAssembly] Implement prototype v128.load{32,64}_zero instructions (details)
  3. [ARM] Convert VPSEL to VMOV in tail predicated loops (details)
  4. [HWASan] [GlobalISel] Add +tagged-globals backend feature for GlobalISel (details)
Commit 66e7dce714fabd3ddb1aed635e4b826476d4f1a2 by 31459023+hctim
Revert "[X86][SSE] Shuffle combine blends to OR(X,Y) if the relevant elements are known zero."

This reverts commit 219f32f4b68679563443cdaae7b8174c9976409a.

Commit contains unsigned compasions that break bots that build with
-Wsign-compare.
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/insertelement-ones.ll (diff)
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v8.ll (diff)
Commit cb327922101b28ea70ec68d7f026da0e5e388eed by tlively
[WebAssembly] Implement prototype v128.load{32,64}_zero instructions

Specified in https://github.com/WebAssembly/simd/pull/237, these
instructions load the first vector lane from memory and zero the other
lanes. Since these instructions are not officially part of the SIMD
proposal, they are only available on an opt-in basis via LLVM
intrinsics and clang builtin functions. If these instructions are
merged to the proposal, this implementation will change so that the
instructions will be generated from normal IR. At that point the
intrinsics and builtin functions would be removed.

This PR also changes the opcodes for the experimental f32x4.qfm{a,s}
instructions because their opcodes conflicted with those of the
v128.load{32,64}_zero instructions. The new opcodes were chosen to
match those used in V8.

Differential Revision: https://reviews.llvm.org/D84820
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td (diff)
The file was modifiedllvm/test/MC/WebAssembly/simd-encodings.s (diff)
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def (diff)
The file was modifiedclang/test/CodeGen/builtins-wasm.c (diff)
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h (diff)
The file was addedllvm/test/CodeGen/WebAssembly/simd-load-zero-offset.ll
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp (diff)
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (diff)
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td (diff)
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (diff)
Commit 22916481c11e1d46132752086290a668e62fc9ce by david.green
[ARM] Convert VPSEL to VMOV in tail predicated loops

VPSEL has slightly different semantics under tail predication (it can
end up selecting from Qn, Qm and Qd). We do not model that at the moment
so they block tail predicated loops from being formed.

This just converts them into a predicated VMOV instead (via a VORR),
allowing tail predication to happen whilst still modelling the original
behaviour of the input.

Differential Revision: https://reviews.llvm.org/D85110
The file was modifiedllvm/lib/Target/ARM/MVEVPTOptimisationsPass.cpp (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vctp.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-selectop3.ll (diff)
Commit 9a05fa10bd05525adedb6117351333699a3d4ae2 by 31459023+hctim
[HWASan] [GlobalISel] Add +tagged-globals backend feature for GlobalISel

GlobalISel is the default ISel for aarch64 at -O0. Prior to D78465, GlobalISel
didn't have support for dealing with address-of-global lowerings, so it fell
back to SelectionDAGISel.

HWASan Globals require special handling, as they contain the pointer tag in the
top 16-bits, and are thus outside the code model. We need to generate a `movk`
in the instruction sequence with a G3 relocation to ensure the bits are
relocated properly. This is implemented in SelectionDAGISel, this patch does
the same for GlobalISel.

GlobalISel and SelectionDAGISel differ in their lowering sequence, so there are
differences in the final instruction sequence, explained in
`tagged-globals.ll`. Both of these implementations are correct, but GlobalISel
is slightly larger code size / slightly slower (by a couple of arithmetic
instructions). I don't see this as a problem for now as GlobalISel is only on
by default at `-O0`.

Reviewed By: aemerson, arsenm

Differential Revision: https://reviews.llvm.org/D82615
The file was modifiedllvm/test/CodeGen/AArch64/tagged-globals.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)
The file was addedcompiler-rt/test/hwasan/TestCases/exported-tagged-global.c