Started 1 mo 22 days ago
Took 57 min

Success Build #13524 (Aug 10, 2020 3:53:45 AM)

Changes
  1. [ScalarizeMaskedMemIntrin][X86] Refresh missed transform test cases from rGc0c3b9a25fee (details / githubweb)
  2. [PowerPC] Add intrinsic to read or set FPSCR register (details / githubweb)
  3. [SyntaxTree] Implement the List construct. (details / githubweb)
  4. [LoopInterchange] Form LCSSA phis for values in orig outer loop header. (details / githubweb)

Started by an SCM change (15 times)

This run spent:

  • 45 min waiting;
  • 57 min build duration;
  • 1 hr 43 min total from scheduled to completion.
Revision: 54cb552b962097d0e3ef7306b69a3c82cc7fff37
  • refs/remotes/origin/master
Revision: 74e099cb9569f67ddb4341839eea408abc67e04e
  • refs/remotes/origin/master
Test Result (no failures)