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Summary

  1. AMDGPU/GlobalISel: Match andn2/orn2 for more types (details)
Commit 40a142fa57d648e3daadfdaa75731360e1ebab2e by arsenm2
AMDGPU/GlobalISel: Match andn2/orn2 for more types

Unfortunately this ends up not working as expected on targets with
16-bit operations due to AMDGPUCodeGenPrepare's promotion of uniform
16-bit ops to i32.

The vector case annoyingly requires switching the checked opcode,
since constants for vectors aren't directly handled.

I also need to think more carefully about whether this is valid for i1.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll (diff)