Started 2 mo 11 days ago
Took 42 min

Success Build #14521 (Sep 14, 2020 11:44:39 AM)

Changes
  1. Fix 132e57bc597bd3f50174b7d286c43f76b47f11c1 (details / githubweb)
  2. [DAGCombiner] Fold fmin/fmax with INF / FLT_MAX (details / githubweb)
  3. [InstCombine] Simplify select operand based on equality condition (details / githubweb)
  4. [ms] [llvm-ml] Add missing built-in type aliases (details / githubweb)
  5. [ms] [llvm-ml] Fix struct padding logic (details / githubweb)
  6. [ms] [llvm-ml] Add support for size queries in MASM (details / githubweb)
  7. [ms] [llvm-ml] Add basic support for SEH, including PROC FRAME (details / githubweb)
  8. [ARM] Add more tests for vecreduce soft float legalization (NFC) (details / githubweb)
  9. [Legalize][ARM][X86] Add float legalization for VECREDUCE (details / githubweb)

Started by an SCM change (17 times)

This run spent:

  • 49 min waiting;
  • 42 min build duration;
  • 1 hr 32 min total from scheduled to completion.
Revision: 53f36f06afbc02d1ab96e3789b41ddeafe31f40e
  • refs/remotes/origin/master
Revision: 29eb67693d9ac60038068870cb44710d81073021
  • refs/remotes/origin/master
Test Result (no failures)