SuccessChanges

Summary

  1. [MCA] Improved cost computation for loop carried dependencies in the (details)
  2. Reapply r372285 "GlobalISel: Don't materialize immarg arguments to (details)
  3. [Float2Int] avoid crashing on unreachable code (PR38502) (details)
  4. [AMDGPU] Unnecessary -amdgpu-scalarize-global-loads=false flag removed (details)
Commit e0900f285bb532790ed494df901f87c5c8b904da by Andrea_DiBiagio
[MCA] Improved cost computation for loop carried dependencies in the
bottleneck analysis.
This patch introduces a cut-off threshold for dependency edge frequences
with the goal of simplifying the critical sequence computation.  This
patch also removes the cost normalization for loop carried dependencies.
We didn't really need to artificially amplify the cost of loop-carried
dependencies since it is already computed as the integral over time of
the delay (in cycle).
In the absence of backend stalls there is no need for computing a
critical sequence. With this patch we early exit from the critical
sequence computation if no bottleneck was reported during the
simulation.
llvm-svn: 372337
The file was modifiedllvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp (diff)
The file was modifiedllvm/tools/llvm-mca/Views/BottleneckAnalysis.h (diff)
The file was modifiedllvm/test/tools/llvm-mca/X86/SkylakeClient/bottleneck-analysis.s (diff)
Commit 3ecab8e4555aee0b4aa10c413696a67f55948c39 by Matthew.Arsenault
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to
intrinsics"
This reverts r372314, reapplying r372285 and the commits which depend on
it (r372286-r372293, and r372296-r372297)
This was missing one switch to getTargetConstant in an untested case.
llvm-svn: 372338
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir (diff)
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir (diff)
The file was modifiedllvm/lib/Target/X86/X86InstrSystem.td (diff)
The file was modifiedllvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td (diff)
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h (diff)
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrFormats.td (diff)
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td (diff)
The file was modifiedllvm/lib/Target/Mips/Mips64InstrInfo.td (diff)
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepOperands.td (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (diff)
The file was modifiedllvm/lib/Target/SystemZ/SystemZOperators.td (diff)
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (diff)
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td (diff)
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAGInstrs.h (diff)
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td (diff)
The file was modifiedllvm/lib/Target/X86/X86InstrTSX.td (diff)
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h (diff)
The file was modifiedllvm/lib/Target/Mips/MipsSEISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (diff)
The file was modifiedllvm/lib/Target/ARM/ARMInstrInfo.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h (diff)
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrVector.td (diff)
The file was modifiedllvm/lib/Target/SystemZ/SystemZPatterns.td (diff)
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll (diff)
The file was modifiedllvm/lib/Target/Mips/MipsDSPInstrInfo.td (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
The file was modifiedllvm/lib/Target/Mips/MipsInstrInfo.td (diff)
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td (diff)
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/Mips/MipsMSAInstrInfo.td (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZOperands.td (diff)
The file was addedllvm/test/TableGen/immarg.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoA.td (diff)
The file was modifiedllvm/lib/Target/X86/X86InstrXOP.td (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td (diff)
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
The file was addedllvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
The file was modifiedllvm/lib/Target/Hexagon/HexagonIntrinsics.td (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td (diff)
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (diff)
The file was modifiedllvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir (diff)
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (diff)
Commit 13e71ce69319d7acdd0e8d57b31c09545d9f2a45 by spatel
[Float2Int] avoid crashing on unreachable code (PR38502)
In the example from: https://bugs.llvm.org/show_bug.cgi?id=38502
...we hit infinite looping/crashing because we have non-standard IR - an
instruction operand is used before defined. This and other unusual
constructs are allowed in unreachable blocks, so avoid the problem by
using DominatorTree to step around landmines.
Differential Revision: https://reviews.llvm.org/D67766
llvm-svn: 372339
The file was modifiedllvm/test/Other/opt-O3-pipeline.ll (diff)
The file was modifiedllvm/include/llvm/Transforms/Scalar/Float2Int.h (diff)
The file was modifiedllvm/test/Other/opt-Os-pipeline.ll (diff)
The file was modifiedllvm/test/Other/opt-O2-pipeline.ll (diff)
The file was modifiedllvm/lib/Transforms/Scalar/Float2Int.cpp (diff)
The file was modifiedllvm/test/Transforms/Float2Int/basic.ll (diff)
Commit e2f9bc3b11baebbdd91ba0ae2faf30d39071ca54 by Alexander.Timofeev
[AMDGPU] Unnecessary -amdgpu-scalarize-global-loads=false flag removed
from min/max lit tests.
Reviewers: arsenm
Differential Revision: https://reviews.llvm.org/D67712
llvm-svn: 372340
The file was modifiedllvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/sminmax.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/max.ll (diff)