Started 1 mo 11 days ago
Took 1 hr 25 min

Success Build #7054 (Feb 21, 2020 12:13:17 PM)

Changes
  1. [mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V. (details / githubweb)
  2. [MLIR] Remove constexpr from LoopOps.td (details / githubweb)
  3. [Hexagon] Simplify intrinsic (vandvrt (vandqrt q b) m) -> q if possible (details / githubweb)
  4. Move StandardOps/Ops.h to StandardOps/IR/Ops.h (details / githubweb)
  5. [llvm][aarch64] SVE addressing modes. (details / githubweb)
  6. [VectorCombine] refactor cost calcs to reduce duplication; NFC (details / githubweb)
  7. [llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics for SVE. (details / githubweb)

Started by an SCM change (16 times)

This run spent:

  • 49 min waiting;
  • 1 hr 25 min build duration;
  • 2 hr 15 min total from scheduled to completion.
Revision: 33bf1196475cbc9b84914c41308cf252764803ee
  • refs/remotes/origin/master
Revision: 3a4296e9c1cdb53e0bf939b244790d257a6d5f26
  • refs/remotes/origin/master
Test Result (no failures)