1. [ELF][ARM] Fix /DISCARD/ of section with .ARM.exidx section (details)
  2. [StructurizeCFG] Enable -structurizecfg-relaxed-uniform-regions by (details)
  3. [TargetLowering] SimplifyMultipleUseDemandedBits - return UNDEF for (details)
Commit 7f320d4bf074047080962b8eb4adf60663cb23e6 by peter.smith
[ELF][ARM] Fix /DISCARD/ of section with .ARM.exidx section
The combineEhSections runs, by design, before processSectionCommands so
that input exception sections like .ARM.exidx and .eh_frame are not
assigned to OutputSections. Unfortunately if /DISCARD/ removes
InputSections that have associated .ARM.exidx sections without
discarding the .ARM.exidx synthetic section then we will end up crashing
when trying to sort the InputSections in ascending address order.
We fix this by filtering out the sections that have been discarded prior
to processing the InputSections in finalizeContents().
fixes pr42890
Differential Revision:
llvm-svn: 368041
The file was addedlld/test/ELF/arm-exidx-partial-discard.s
The file was modifiedlld/ELF/SyntheticSections.cpp (diff)
Commit 5a0794327a6756ec904dfdc1d8015d510ee49526 by tpr.llvm
[StructurizeCFG] Enable -structurizecfg-relaxed-uniform-regions by
D62198 introduced an option to relax the checks for
hasOnlyUniformBranches. This commit turns the option on by default, for
better code generation in some cases in AMDGPU.
Differential Revision:
Change-Id: I9cbff002a1e74d3b7eb96b4192dc8129936d537d llvm-svn: 368042
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-optnone.ll (diff)
The file was modifiedllvm/lib/Transforms/Scalar/StructurizeCFG.cpp (diff)
Commit dae5ddad9d1954c44a51c4b7bc8be1a5fb61a203 by llvm-dev
[TargetLowering] SimplifyMultipleUseDemandedBits - return UNDEF for
undemanded ops
If we demand no bits/elts from an Op, just return UNDEF
llvm-svn: 368043
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-mul.ll (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-mul-widen.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-udiv-128.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/packss.ll (diff)