Started 11 days ago
Took 4 hr 59 min on green-dragon-02

Failed Build #14363 (Jul 9, 2019 12:05:18 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 365538
  • http://llvm.org/svn/llvm-project/cfe/trunk : 365528
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 365534
  • http://llvm.org/svn/llvm-project/zorg/trunk : 365440
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 365359
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 365531
Changes
  1. [PoisonChecking] Add validation rules for "exact" on sdiv/udiv

    As directly stated in the LangRef, no ambiguity here... (detail)
    by reames
  2. [ThinLTO] only emit used or referenced CFI records to index

    Summary: We emit CFI_FUNCTION_DEFS and CFI_FUNCTION_DECLS to
    distributed ThinLTO indices to implement indirect function call
    checking.  This change causes us to only emit entries for functions
    that are either defined or used by the module we're writing the index
    for (instead of all functions in the combined index), which can make
    the indices substantially smaller.

    Fixes PR42378.

    Reviewers: pcc, vitalybuka, eugenis

    Subscribers: mehdi_amini, hiraditya, dexonsmith, arphaman, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D63887 (detail)
    by inglorion
  3. Add a transform pass to make the executable semantics of poison explicit in the IR

    Implements a transform pass which instruments IR such that poison semantics are made explicit. That is, it provides a (possibly partial) executable semantics for every instruction w.r.t. poison as specified in the LLVM LangRef. There are obvious parallels to the sanitizer tools, but this pass is focused purely on the semantics of LLVM IR, not any particular source language.

    The target audience for this tool is developers working on or targetting LLVM from a frontend. The idea is to be able to take arbitrary IR (with the assumption of known inputs), and evaluate it concretely after having made poison semantics explicit to detect cases where either a) the original code executes UB, or b) a transform pass introduces UB which didn't exist in the original program.

    At the moment, this is mostly the framework and still needs to be fleshed out. By reusing existing code we have decent coverage, but there's a lot of cases not yet handled. What's here is good enough to handle interesting cases though; for instance, one of the recent LFTR bugs involved UB being triggered by integer induction variables with nsw/nuw flags would be reported by the current code.

    (See comment in PoisonChecking.cpp for full explanation and context)

    Differential Revision: https://reviews.llvm.org/D64215 (detail)
    by reames
  4. Try to appease the Windows build bots.

    Several of the conditonal operators commited in llvm-svn: 365524 fail to compile
    on the windows buildbots. Converting to an if and early return to try to fix. (detail)
    by sfertile
  5. Revert "[TSan] Improve handling of stack pointer mangling in {set,long}jmp, pt.8"

    This reverts commit 521f77e6351fd921f5a81027c7c72addca378989. (detail)
    by yln
  6. [BPF] Fix a typo in the file name

    Fixed the file name from BPFAbstrctMemberAccess.cpp to
    BPFAbstractMemberAccess.cpp.

    Signed-off-by: Yonghong Song <yhs@fb.com> (detail)
    by yhs
  7. [clangd] Rewrite of logic to rebuild the background index serving structures.

    Summary:
    Previously it was rebuilding every 5s by default, which was much too frequent
    in the long run - the goal was to provide an early build. There were also some
    bugs. There were also some bugs, and a dedicated thread was used in production
    but not tested.

    - rebuilds are triggered by #TUs built, rather than time. This should scale
       more sensibly to fast vs slow machines.
    - there are two separate indexed-TU thresholds to trigger index build: 5 TUs
       for the first build, 100 for subsequent rebuilds.
    - rebuild is always done on the regular indexing threads, and is affected by
       blockUntilIdle. This means unit/lit tests run the production configuration.
    - fixed a bug where we'd rebuild after attempting to load shards, even if there
       were no shards.
    - the BackgroundIndexTests don't really test the subtleties of the rebuild
       policy (for determinism, we call blockUntilIdle, so rebuild-on-idle is enough
       to pass the tests). Instead, we expose the rebuilder as a separate class and
       have fine-grained tests for it.

    Reviewers: kadircet

    Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, jfb, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64291 (detail)
    by sammccall
  8. gn build: Merge r365503. (detail)
    by pcc
  9. [unittest] Add the missing bogus machine register info initialization. (detail)
    by hliao
  10. [AMDGPU] gfx908 clang target

    Differential Revision: https://reviews.llvm.org/D64430 (detail)
    by rampitec
  11. [AMDGPU] gfx908 target

    Differential Revision: https://reviews.llvm.org/D64429 (detail)
    by rampitec
  12. [Object][XCOFF] Add support for 64-bit file header and section header dumping.

    Adds a readobj dumper for 32-bit and 64-bit section header tables, and extend
    support for the file-header dumping to include 64-bit object files. Also
    refactors the binary file parsing to be done in a helper function in an attempt
    to cleanup error handeling.

    Differential Revision: https://reviews.llvm.org/D63843 (detail)
    by sfertile
  13. [InstCombine] add tests for trunc(load); NFC

    I'm not sure if transforming any of these is valid as
    a target-independent fold, but we might as well have
    a few tests here to confirm or deny our position. (detail)
    by spatel
  14. [clangd] Show documentation in hover, and fetch docs from index if needed.

    Summary:
    I assume showing docs is going to be part of structured hover rendering, but
    it's unclear whether that's going to make clangd 9 so this is low-hanging fruit.

    (Also fixes a bug uncovered in FormattedString's plain text output: need blank
    lines when text follows codeblocks)

    Reviewers: kadircet

    Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64296 (detail)
    by sammccall
  15. AMDGPU: Fix test failing since r365512 (detail)
    by arsenm
  16. Revert "[HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfitable()"

    This reverts commit d95557306585404893d610784edb3e32f1bfce18. (detail)
    by jsji
  17. Add lit.local.cfg to llvm-objdump tests

    Add configuration file to llvm-objdump tests to treat files with .yaml
    extension as tests. (detail)
    by steven_wu
  18. [ObjC] Add a warning for implicit conversions of a constant non-boolean value to BOOL

    rdar://51954400

    Differential revision: https://reviews.llvm.org/D63912 (detail)
    by epilk
  19. Remove a comment that has been obsolete since r327679 (detail)
    by nico
  20. [unittest] Add bogus register info.

    Reviewers: dstenb

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64421 (detail)
    by hliao
  21. Rename llvm/test/tools/llvm-pdbdump to llvm/test/tools/llvm-pdbutil

    llvm-pdbdump was renamed to llvm-pdbutil long ago. This updates the test
    to be where you'd expect them to be. (detail)
    by nico
  22. Make pdbdump-objfilename test work again

    - The test had extension .yaml, which lit doesn't execute in this
      directory. Rename to .test to make it run, and move the yaml bits
      into a dedicated file, like with all other tests in this dir.

    - llvm-pdbdump got renamed to llvm-pdbutil long ago, update test.

    - -dbi-module-info got renamed in r305032, update test for this too. (detail)
    by nico
  23. [TSan] Improve handling of stack pointer mangling in {set,long}jmp, pt.8

    Refine longjmp key management.  For Linux, re-implement key retrieval in
    C (instead of assembly).  Removal of `InitializeGuardPtr` and a final
    round of cleanups will be done in the next commit.

    Reviewed By: dvyukov

    Differential Revision: https://reviews.llvm.org/D64092 (detail)
    by yln
  24. [AMDGPU] Created a sub-register class for the return address operand in the return instruction.

    Function return instruction lowering, currently uses the fixed register pair s[30:31] for holding
    the return address. It can be any SGPR pair other than the CSRs. Created an SGPR pair sub-register class
    exclusive of the CSRs, and used this regclass while lowering the return instruction.

    Reviewed By: arsenm

    Differential Revision: https://reviews.llvm.org/D63924 (detail)
    by cdevadas
  25. [RISCV] Fix ICE in isDesirableToCommuteWithShift

    Summary:
    There was an error being thrown from isDesirableToCommuteWithShift in
    some tests. This was tracked down to the method being called before
    legalisation, with an extended value type, not a machine value type.

    In the case I diagnosed, the error was only hit with an instruction sequence
    involving `i24`s in the add and shift. `i24` is not a Machine ValueType, it is
    instead an Extended ValueType which was causing the issue.

    I have added a test to cover this case, and fixed the error in the callback.

    Reviewers: asb, luismarques

    Reviewed By: asb

    Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64425 (detail)
    by lenary
  26. [AArch64][GlobalISel] Optimize conditional branches followed by unconditional branches

    If we have an icmp->brcond->br sequence where the brcond just branches to the
    next block jumping over the br, while the br takes the false edge, then we can
    modify the conditional branch to jump to the br's target while inverting the
    condition of the incoming icmp. This means we can eliminate the br as an
    unconditional branch to the fallthrough block.

    Differential Revision: https://reviews.llvm.org/D64354 (detail)
    by aemerson
  27. Revert Revert Devirtualize destructor of final class.

    Revert r364359 and recommit r364100.

    r364100 was reverted as r364359 due to an internal test failure, but it was a
    false alarm. (detail)
    by yamauchi
  28. [mips] Show error in case of using FP64 mode on pre MIPS32R2 CPU (detail)
    by atanasyan
  29. [mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC

    Support for 64-bit coprocessors on a 32-bit architecture
    was added in `MIPS32 R2`. (detail)
    by atanasyan
  30. [NFC] Fixed tests (detail)
    by xbolva00
  31. [DAGCombine] LoadedSlice - keep getOffsetFromBase() uint64_t offset. NFCI.

    Keep the uint64_t type from getOffsetFromBase() to stop truncation/extension overflow warnings in MSVC in alignment math. (detail)
    by rksimon
  32. [BPF] Support for compile once and run everywhere

    Introduction
    ============

    This patch added intial support for bpf program compile once
    and run everywhere (CO-RE).

    The main motivation is for bpf program which depends on
    kernel headers which may vary between different kernel versions.
    The initial discussion can be found at https://lwn.net/Articles/773198/.

    Currently, bpf program accesses kernel internal data structure
    through bpf_probe_read() helper. The idea is to capture the
    kernel data structure to be accessed through bpf_probe_read()
    and relocate them on different kernel versions.

    On each host, right before bpf program load, the bpfloader
    will look at the types of the native linux through vmlinux BTF,
    calculates proper access offset and patch the instruction.

    To accommodate this, three intrinsic functions
       preserve_{array,union,struct}_access_index
    are introduced which in clang will preserve the base pointer,
    struct/union/array access_index and struct/union debuginfo type
    information. Later, bpf IR pass can reconstruct the whole gep
    access chains without looking at gep itself.

    This patch did the following:
      . An IR pass is added to convert preserve_*_access_index to
        global variable who name encodes the getelementptr
        access pattern. The global variable has metadata
        attached to describe the corresponding struct/union
        debuginfo type.
      . An SimplifyPatchable MachineInstruction pass is added
        to remove unnecessary loads.
      . The BTF output pass is enhanced to generate relocation
        records located in .BTF.ext section.

    Typical CO-RE also needs support of global variables which can
    be assigned to different values to different hosts. For example,
    kernel version can be used to guard different versions of codes.
    This patch added the support for patchable externals as well.

    Example
    =======

    The following is an example.

      struct pt_regs {
        long arg1;
        long arg2;
      };
      struct sk_buff {
        int i;
        struct net_device *dev;
      };

      #define _(x) (__builtin_preserve_access_index(x))
      static int (*bpf_probe_read)(void *dst, int size, const void *unsafe_ptr) =
              (void *) 4;
      extern __attribute__((section(".BPF.patchable_externs"))) unsigned __kernel_version;
      int bpf_prog(struct pt_regs *ctx) {
        struct net_device *dev = 0;

        // ctx->arg* does not need bpf_probe_read
        if (__kernel_version >= 41608)
          bpf_probe_read(&dev, sizeof(dev), _(&((struct sk_buff *)ctx->arg1)->dev));
        else
          bpf_probe_read(&dev, sizeof(dev), _(&((struct sk_buff *)ctx->arg2)->dev));
        return dev != 0;
      }

    In the above, we want to translate the third argument of
    bpf_probe_read() as relocations.

      -bash-4.4$ clang -target bpf -O2 -g -S trace.c

    The compiler will generate two new subsections in .BTF.ext,
    OffsetReloc and ExternReloc.
    OffsetReloc is to record the structure member offset operations,
    and ExternalReloc is to record the external globals where
    only u8, u16, u32 and u64 are supported.

       BPFOffsetReloc Size
       struct SecLOffsetReloc for ELF section #1
       A number of struct BPFOffsetReloc for ELF section #1
       struct SecOffsetReloc for ELF section #2
       A number of struct BPFOffsetReloc for ELF section #2
       ...
       BPFExternReloc Size
       struct SecExternReloc for ELF section #1
       A number of struct BPFExternReloc for ELF section #1
       struct SecExternReloc for ELF section #2
       A number of struct BPFExternReloc for ELF section #2

      struct BPFOffsetReloc {
        uint32_t InsnOffset;    ///< Byte offset in this section
        uint32_t TypeID;        ///< TypeID for the relocation
        uint32_t OffsetNameOff; ///< The string to traverse types
      };

      struct BPFExternReloc {
        uint32_t InsnOffset;    ///< Byte offset in this section
        uint32_t ExternNameOff; ///< The string for external variable
      };

    Note that only externs with attribute section ".BPF.patchable_externs"
    are considered for Extern Reloc which will be patched by bpf loader
    right before the load.

    For the above test case, two offset records and one extern record
    will be generated:
      OffsetReloc records:
            .long   .Ltmp12                 # Insn Offset
            .long   7                       # TypeId
            .long   242                     # Type Decode String
            .long   .Ltmp18                 # Insn Offset
            .long   7                       # TypeId
            .long   242                     # Type Decode String

      ExternReloc record:
            .long   .Ltmp5                  # Insn Offset
            .long   165                     # External Variable

      In string table:
            .ascii  "0:1"                   # string offset=242
            .ascii  "__kernel_version"      # string offset=165

    The default member offset can be calculated as
        the 2nd member offset (0 representing the 1st member) of struct "sk_buff".

    The asm code:
        .Ltmp5:
        .Ltmp6:
                r2 = 0
                r3 = 41608
        .Ltmp7:
        .Ltmp8:
                .loc    1 18 9 is_stmt 0        # t.c:18:9
        .Ltmp9:
                if r3 > r2 goto LBB0_2
        .Ltmp10:
        .Ltmp11:
                .loc    1 0 9                   # t.c:0:9
        .Ltmp12:
                r2 = 8
        .Ltmp13:
                .loc    1 19 66 is_stmt 1       # t.c:19:66
        .Ltmp14:
        .Ltmp15:
                r3 = *(u64 *)(r1 + 0)
                goto LBB0_3
        .Ltmp16:
        .Ltmp17:
        LBB0_2:
                .loc    1 0 66 is_stmt 0        # t.c:0:66
        .Ltmp18:
                r2 = 8
                .loc    1 21 66 is_stmt 1       # t.c:21:66
        .Ltmp19:
                r3 = *(u64 *)(r1 + 8)
        .Ltmp20:
        .Ltmp21:
        LBB0_3:
                .loc    1 0 66 is_stmt 0        # t.c:0:66
                r3 += r2
                r1 = r10
        .Ltmp22:
        .Ltmp23:
        .Ltmp24:
                r1 += -8
                r2 = 8
                call 4

    For instruction .Ltmp12 and .Ltmp18, "r2 = 8", the number
    8 is the structure offset based on the current BTF.
    Loader needs to adjust it if it changes on the host.

    For instruction .Ltmp5, "r2 = 0", the external variable
    got a default value 0, loader needs to supply an appropriate
    value for the particular host.

    Compiling to generate object code and disassemble:
       0000000000000000 bpf_prog:
               0:       b7 02 00 00 00 00 00 00         r2 = 0
               1:       7b 2a f8 ff 00 00 00 00         *(u64 *)(r10 - 8) = r2
               2:       b7 02 00 00 00 00 00 00         r2 = 0
               3:       b7 03 00 00 88 a2 00 00         r3 = 41608
               4:       2d 23 03 00 00 00 00 00         if r3 > r2 goto +3 <LBB0_2>
               5:       b7 02 00 00 08 00 00 00         r2 = 8
               6:       79 13 00 00 00 00 00 00         r3 = *(u64 *)(r1 + 0)
               7:       05 00 02 00 00 00 00 00         goto +2 <LBB0_3>

        0000000000000040 LBB0_2:
               8:       b7 02 00 00 08 00 00 00         r2 = 8
               9:       79 13 08 00 00 00 00 00         r3 = *(u64 *)(r1 + 8)

        0000000000000050 LBB0_3:
              10:       0f 23 00 00 00 00 00 00         r3 += r2
              11:       bf a1 00 00 00 00 00 00         r1 = r10
              12:       07 01 00 00 f8 ff ff ff         r1 += -8
              13:       b7 02 00 00 08 00 00 00         r2 = 8
              14:       85 00 00 00 04 00 00 00         call 4

    Instructions #2, #5 and #8 need relocation resoutions from the loader.

    Signed-off-by: Yonghong Song <yhs@fb.com>

    Differential Revision: https://reviews.llvm.org/D61524 (detail)
    by yhs
  33. [ADT] Remove MSVC-only "no two-phase name lookup" typename path.

    Now that we've dropped VS2015 support (D64326) we can use the regular codepath as VS2017+ correctly handles it (detail)
    by rksimon
  34. [NFC] Added tests for D64285 (detail)
    by xbolva00
  35. [OpenCL][Sema] Improve address space support for blocks

    Summary:
    This patch ensures that the following code is compiled identically with
    -cl-std=CL2.0 and -fblocks -cl-std=c++.

        kernel void test(void) {
          void (^const block_A)(void) = ^{
            return;
          };
        }

    A new test is not added because cl20-device-side-enqueue.cl will cover
    this once blocks are further improved for C++ for OpenCL.

    The changes to Sema::PerformImplicitConversion are based on
    the parts of Sema::CheckAssignmentConstraints on block pointer
    conversions.

    Reviewers: rjmccall, Anastasia

    Subscribers: yaxunl, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64083 (detail)
    by mantognini
  36. [OpenCL][Sema] Fix builtin rewriting

    This patch ensures built-in functions are rewritten using the proper
    parent declaration.

    Existing tests are modified to run in C++ mode to ensure the
    functionality works also with C++ for OpenCL while not increasing the
    testing runtime. (detail)
    by mantognini
  37. Ignore trailing NullStmts in StmtExprs for GCC compatibility.

    Ignore trailing NullStmts in compound expressions when determining the result type and value. This is to match the GCC behavior which ignores semicolons at the end of compound expressions.

    Patch by Dominic Ferreira. (detail)
    by aaronballman
  38. [HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfitable()

    Differential Revision: https://reviews.llvm.org/D64197 (detail)
    by shchenz
  39. [ARM] Add test for MVE and no floats. NFC

    Adds a simple test that MVE with no floating point will be promoted correctly
    to software float calls. (detail)
    by dmgreen
  40. [InferFunctionAttrs] add more tests for derefenceable; NFC (detail)
    by spatel
  41. [MIPS GlobalISel] Register bank select for G_PHI. Select i64 phi

    Select gprb or fprb when def/use register operand of G_PHI is
    used/defined by either:
    copy to/from physical register or
    instruction with only one mapping available for that use/def operand.

    Integer s64 phi is handled with narrowScalar when mapping is applied,
    produced artifacts are combined away. Manually set gprb to all register
    operands of instructions created during narrowScalar.

    Differential Revision: https://reviews.llvm.org/D64351 (detail)
    by petar.avramovic
  42. AMDGPU/GlobalISel: Prepare some tests for store selection

    Mostsly these would fail due to trying to use SI with a flat
    operation. Implementing global loads with MUBUF is more work than
    flat, so these won't be handled in the initial load selection.

    Others fail because store of s64 won't initially work, as the current
    set of patterns expect everything to be turned into v2i32. (detail)
    by arsenm
  43. [MIPS GlobalISel] Regbanks for G_SELECT. Select i64, f32 and f64 select

    Select gprb or fprb when def/use register operand of G_SELECT is
    used/defined by either:
    copy to/from physical register or
    instruction with only one mapping available for that use/def operand.

    Integer s64 select is handled with narrowScalar when mapping is applied,
    produced artifacts are combined away. Manually set gprb to all register
    operands of instructions created during narrowScalar.

    For selection of floating point s32 or s64 select it is enough to set
    fprb of appropriate size and selectImpl will do the rest.

    Differential Revision: https://reviews.llvm.org/D64350 (detail)
    by petar.avramovic
  44. AMDGPU/GlobalISel: Fix test (detail)
    by arsenm
  45. [libclang] Fix hang in release / assertion in debug when evaluating value-dependent types.

    Expression evaluator doesn't work in value-dependent types, so ensure that the
    precondition it asserts holds.

    This fixes https://bugs.llvm.org/show_bug.cgi?id=42532

    Differential Revision: https://reviews.llvm.org/D64409 (detail)
    by emilio
  46. [docs][llvm-dwarfdump] Fix wording (detail)
    by jhenderson
  47. AMDGPU/GlobalISel: Legalize more concat_vectors (detail)
    by arsenm
  48. AMDGPU/GlobalISel: Improve regbankselect for icmp s16

    Account for 64-bit scalar eq/ne when available. (detail)
    by arsenm
  49. AMDGPU/GlobalISel: Make s16 G_ICMP legal (detail)
    by arsenm
  50. [OPENMP]Fix the float point semantics handling on the device.

    The device should use the same float point representation as the host.
    Previous patch fixed the handling of the sizes of the float point types,
    but did not fixed the fp semantics. This patch makes target device to
    use the host fp semantics. this is required for the correct data
    transfer between host and device and correct codegen. (detail)
    by abataev
  51. AMDGPU/GlobalISel: Select G_SUB (detail)
    by arsenm
  52. AMDGPU/GlobalISel: Select G_UNMERGE_VALUES (detail)
    by arsenm
  53. AMDGPU/GlobalISel: Select G_MERGE_VALUES (detail)
    by arsenm
  54. gn build: Merge r365453 (detail)
    by nico

Started by timer (5 times)

This run spent:

  • 4 hr 54 min waiting;
  • 4 hr 59 min build duration;
  • 9 hr 53 min total from scheduled to completion.
Test Result (2 failures / -3)

Identified problems

Assertion failure

This build failed because of an assertion failure. Below is a list of all errors in the build log:
Indication 1

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 2

Ninja target failed

Below is a link to the first failed ninja target.
Indication 3