Started 7 days 6 hr ago
Took 5 hr 17 min on green-dragon-02

Failed Build #14663 (Sep 9, 2019 3:50:32 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 371465
  • http://llvm.org/svn/llvm-project/cfe/trunk : 371451
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 371453
  • http://llvm.org/svn/llvm-project/zorg/trunk : 371154
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 371324
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 371422
Changes
  1. [GlobalISel]: Fix a bug where we could dereference None

    getConstantVRegVal returns None when dealing with constants > 64 bits.
    Don't assume we always have a value in GISelKnownBits. (detail)
    by aditya_nandakumar
  2. Simplify demangler rule for lambda-expressions to match discussion on
    cxx-abi list. (detail)
    by rsmith
  3. LangRef: mention MSan's problem with speculative conditional branches.

    Summary:
    This short blurb aims to disallow optimizations like we had to revert
    (under MSan) in
      https://reviews.llvm.org/D21165
      https://bugs.llvm.org/show_bug.cgi?id=28054
      https://reviews.llvm.org/D67205

    Reviewers: vitalybuka, efriedma

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67244 (detail)
    by eugenis
  4. [Tests] Fix a typo in a test (detail)
    by reames
  5. [Tests] Precommit test case for D67372 (detail)
    by reames
  6. Fix MSVC "not all control paths return a value" warning. NFCI. (detail)
    by rksimon
  7. [UBSan] Follow up fix for r371442.

    Reviewers: vitalybuka, hctim, Dor1s

    Reviewed By: Dor1s

    Subscribers: delcypher, #sanitizers, llvm-commits

    Tags: #llvm, #sanitizers

    Differential Revision: https://reviews.llvm.org/D67371 (detail)
    by dor1s
  8. [LoopVectorize] Leverage speculation safety to avoid masked.loads

    If we're vectorizing a load in a predicated block, check to see if the load can be speculated rather than predicated.  This allows us to generate a normal vector load instead of a masked.load.

    To do so, we must prove that all bytes accessed on any iteration of the original loop are dereferenceable, and that all loads (across all iterations) are properly aligned.  This is equivelent to proving that hoisting the load into the loop header in the original scalar loop is safe.

    Note: There are a couple of code motion todos in the code.  My intention is to wait about a day - to be sure this sticks - and then perform the NFC motion without furthe review.

    Differential Revision: https://reviews.llvm.org/D66688 (detail)
    by reames
  9. [analyzer] NFC: Simplify bug report equivalence classes to not be ilists.

    Use a vector of unique pointers instead.

    Differential Revision: https://reviews.llvm.org/D67024 (detail)
    by dergachev
  10. [analyzer] NFC: Introduce sub-classes for path-sensitive and basic reports.

    Checkers are now required to specify whether they're creating a
    path-sensitive report or a path-insensitive report by constructing an
    object of the respective type.

    This makes BugReporter more independent from the rest of the Static Analyzer
    because all Analyzer-specific code is now in sub-classes.

    Differential Revision: https://reviews.llvm.org/D66572 (detail)
    by dergachev
  11. [Tests] Add anyextend tests for unordered atomics

    Motivated by work on changing our representation of unordered atomics in SelectionDAG, but as an aside, all our lowerings for O3 are terrible.  Even the ones which ignore the atomicity. (detail)
    by reames
  12. Relax opcode checks in test to check for only a number instead of a specific number. (detail)
    by dyung
  13. [TSan] Add AnnotateIgnoreReadsBegin declaration to tsan/test.h

    Declare the family of AnnotateIgnore[Read,Write][Begin,End] TSan
    annotations in compiler-rt/test/tsan/test.h so that we don't have to
    declare them separately in every test that needs them.  Replace usages.

    Leave usages that explicitly test the annotation mechanism:
      thread_end_with_ignore.cpp
      thread_end_with_ignore3.cpp (detail)
    by yln
  14. [SDAG] Add a isSimple cover functon to MemSDNode, just as we have in IR/MI [NFC]

    Uses are in reviews D66322 and D66318.  Submitted separately to control rebuild times. (detail)
    by reames
  15. [Driver] Handle default case in refactored addOpenMPRuntime

    Summary:
    Appease failed builds (due to -Werror and -Wswitch) where OMPRT_Unknown
    is not handled in the switch statement (even though it's handled by the
    early exit).

    This fixes -Wswitch triggered by r371442.

    Reviewers: srhines, danalbert, jdoerfert

    Subscribers: guansong, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D67364 (detail)
    by pirama
  16. [Remarks] Fix warning for uint8_t < 0 comparison

    http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/19109/steps/build-stage1-compiler/logs/stdio (detail)
    by thegameg
  17. [UBSan] Do not overwrite the default print_summary sanitizer option.

    Summary:
    This option is true by default in sanitizer common. The default
    false value was added a while ago without any reasoning in
    https://github.com/llvm-mirror/compiler-rt/commit/524e934112a593ac081bf2b05aa0d60a67987f05

    so, presumably it's safe to remove for consistency.

    Reviewers: hctim, samsonov, morehouse, kcc, vitalybuka

    Reviewed By: hctim, samsonov, vitalybuka

    Subscribers: delcypher, #sanitizers, llvm-commits, kcc

    Tags: #llvm, #sanitizers

    Differential Revision: https://reviews.llvm.org/D67193 (detail)
    by dor1s
  18. Introduce infrastructure for an incremental port of SelectionDAG atomic load/store handling

    This is the first patch in a large sequence. The eventual goal is to have unordered atomic loads and stores - and possibly ordered atomics as well - handled through the normal ISEL codepaths for loads and stores. Today, there handled w/instances of AtomicSDNodes. The result of which is that all transforms need to be duplicated to work for unordered atomics. The benefit of the current design is that it's harder to introduce a silent miscompile by adding an transform which forgets about atomicity.  See the thread on llvm-dev titled "FYI: proposed changes to atomic load/store in SelectionDAG" for further context.

    Note that this patch is NFC unless the experimental flag is set.

    The basic strategy I plan on taking is:

        introduce infrastructure and a flag for testing (this patch)
        Audit uses of isVolatile, and apply isAtomic conservatively*
        piecemeal conservative* update generic code and x86 backedge code in individual reviews w/tests for cases which didn't check volatile, but can be found with inspection
        flip the flag at the end (with minimal diffs)
        Work through todo list identified in (2) and (3) exposing performance ops

    (*) The "conservative" bit here is aimed at minimizing the number of diffs involved in (4). Ideally, there'd be none. In practice, getting it down to something reviewable by a human is the actual goal. Note that there are (currently) no paths which produce LoadSDNode or StoreSDNode with atomic MMOs, so we don't need to worry about preserving any behaviour there.

    We've taken a very similar strategy twice before with success - once at IR level, and once at the MI level (post ISEL).

    Differential Revision: https://reviews.llvm.org/D66309 (detail)
    by reames
  19. AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR v2s16

    Handle it the same way as G_BUILD_VECTOR_TRUNC. Arguably only
    G_BUILD_VECTOR_TRUNC should be legal for this, but G_BUILD_VECTOR will
    probably be more convenient in most cases. (detail)
    by arsenm
  20. [TSan] Add interceptors for mach_vm_[de]allocate

    I verified that the test is red without the interceptors.

    rdar://40334350

    Reviewed By: kubamracek, vitalybuka

    Differential Revision: https://reviews.llvm.org/D66616 (detail)
    by yln
  21. AMDGPU: Make VReg_1 size be 1

    This was getting chosen as the preferred 32-bit register class based
    on how TableGen selects subregister classes. (detail)
    by arsenm
  22. [Driver] Add -static-openmp driver option

    Summary:
    For Gnu, FreeBSD and NetBSD, this option forces linking with the static
    OpenMP host runtime (similar to -static-libgcc and -static-libstdcxx).

    Android's NDK will start the shared OpenMP runtime in addition to the static
    libomp.  In this scenario, the linker will prefer to use the shared library by
    default.  Add this option to enable linking with the static libomp.

    Reviewers: Hahnfeld, danalbert, srhines, joerg, jdoerfert

    Subscribers: guansong, cfe-commits

    Tags: #clang

    Fixes https://github.com/android-ndk/ndk/issues/1028

    Differential Revision: https://reviews.llvm.org/D67200 (detail)
    by pirama
  23. AMDGPU/GlobalISel: Select llvm.amdgcn.class

    Also fixes missing SubtargetPredicate on f16 class instructions. (detail)
    by arsenm
  24. AMDGPU/GlobalISel: Select fmed3 (detail)
    by arsenm
  25. [IfConversion] Correctly handle cases where analyzeBranch fails.

    If analyzeBranch fails, on some targets, the out parameters point to
    some blocks in the function. But we can't use that information, so make
    sure to clear it out.  (In some places in IfConversion, we assume that
    any block with a TrueBB is analyzable.)

    The change to the testcase makes it trigger a bug on builds without this
    fix: IfConvertDiamond tries to perform a followup "merge" operation,
    which isn't legal, and we somehow end up with a branch to a deleted MBB.
    I'm not sure how this doesn't crash the compiler.

    Differential Revision: https://reviews.llvm.org/D67306 (detail)
    by efriedma
  26. [x86] add test for false dependency with minsize (PR43239); NFC (detail)
    by spatel
  27. AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsics

    This enables GlobalISel to handle various intrinsics. The custom node
    pattern will be ignored, and the intrinsic will work. This will also
    allow SelectionDAG to directly select the intrinsics, but as they are
    all custom lowered to the nodes, this ends up leaving dead code in the
    table.

    Eventually either GlobalISel should add the equivalent of custom nodes
    equivalent, or intrinsics should be directly used. These each have
    different tradeoffs.

    There are a few more to handle, but these are easy to handle
    ones. Some others fail for other reasons. (detail)
    by arsenm
  28. [SelectionDAG] Remove ISD::FP_ROUND_INREG

    I don't think anything in tree creates this node. So all of this
    code appears to be dead.

    Code coverage agrees
    http://lab.llvm.org:8080/coverage/coverage-reports/llvm/coverage/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp.html

    Differential Revision: https://reviews.llvm.org/D67312 (detail)
    by ctopper
  29. [X86] Allow _MM_FROUND_CUR_DIRECTION and _MM_FROUND_NO_EXC to be used together on instructions that only support SAE and not embedded rounding.

    Current for SAE instructions we only allow _MM_FROUND_CUR_DIRECTION(bit 2) or _MM_FROUND_NO_EXC(bit 3) to be used as the immediate passed to the inrinsics. But these instructions don't perform rounding so _MM_FROUND_CUR_DIRECTION is just sort of a default placeholder when you don't want to suppress exceptions. Using _MM_FROUND_NO_EXC by itself is really bit equivalent to (_MM_FROUND_NO_EXC | _MM_FROUND_TO_NEAREST_INT) since _MM_FROUND_TO_NEAREST_INT is 0. Since we aren't rounding on these instructions we should also accept (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_NO_EXC) as equivalent to (_MM_FROUND_NO_EXC). icc allows this, but gcc does not.

    Differential Revision: https://reviews.llvm.org/D67289 (detail)
    by ctopper
  30. [Remarks] Add parser for bitstream remarks

    The bitstream remark serializer landed in r367372.

    This adds a bitstream remark parser that parser bitstream remark files
    to llvm::remarks::Remark objects through the RemarkParser interface.

    A few interesting things to point out:

    * There are parsing helpers to parse the different types of blocks
    * The main parsing helper allows us to parse remark metadata and open an
    external file containing the encoded remarks
    * This adds a dependency from the Remarks library to the BitstreamReader
    library
    * The testing strategy is to create a remark entry through YAML, parse
    it, serialize it to bitstream, parse that back and compare the objects.
    * There are close to no tests for malformed bitstream remarks, due to
    the lack of textual format for the bitstream format.
    * This adds a new C API for parsing bitstream remarks:
    LLVMRemarkParserCreateBitstream.
    * This bumps the REMARKS_API_VERSION to 1.

    Differential Revision: https://reviews.llvm.org/D67134 (detail)
    by thegameg
  31. [mips] Fix decoding of microMIPS JALX instruction

    microMIPS jump and link exchange instruction stores a target in a
    26-bits field. Despite other microMIPS JAL instructions these bits
    are target address shifted right 2 bits [1]. The patch fixes the
    JALX instruction decoding and uses 2-bit shift.

    [1] MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set

    Differential Revision: https://reviews.llvm.org/D67320 (detail)
    by atanasyan

Started by timer (5 times)

This run spent:

  • 4 hr 39 min waiting;
  • 5 hr 17 min build duration;
  • 9 hr 56 min total from scheduled to completion.
Test Result (1 failure / +1)

Identified problems

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 1

Compile Error

This build failed because of a compile error. Below is a list of all errors in the build log:
Indication 2