FailedChanges

Summary

  1. [RISCV] Support stack offset exceed 32-bit for RV64 Differential Revision: https://reviews.llvm.org/D61884
  2. For PR17164: split -fno-lax-vector-conversion into three different levels: -- none: no lax vector conversions [new GCC default] -- integer: only conversions between integer vectors [old GCC default] -- all: all conversions between same-size vectors [Clang default] For now, Clang still defaults to "all" mode, but per my proposal on cfe-dev (2019-04-10) the default will be changed to "integer" as soon as that doesn't break lots of testcases. (Eventually I'd like to change the default to "none" to match GCC and general sanity.) Following GCC's behavior, the driver flag -flax-vector-conversions is translated to -flax-vector-conversions=integer.
  3. AMDGPU/GlobalISel: Legalize G_FFLOOR
  4. Temporarily revert r371640 "LiveIntervals: Split live intervals on multiple dead defs". It reveals a miscompile on Hexagon. See PR43302 for details.
  5. AMDGPU/GlobalISel: Legalize G_FMAD Unlike SelectionDAG, treat this as a normally legalizable operation. In SelectionDAG this is supposed to only ever formed if it's legal, but I've found that to be restricting. For AMDGPU this is contextually legal depending on whether denormal flushing is allowed in the use function. Technically we currently treat the denormal mode as a subtarget feature, so custom lowering could be avoided. However I consider this to be a defect, and this should be contextually dependent on the controllable rounding mode of the parent function.
  6. Revert r371785. r371785 is causing fails on clang-hexagon-elf buildbots.
  7. AMDGPU/GlobalISel: Select G_CTPOP
  8. DAG/GlobalISel: Correct type profile of bitcount ops The result integer does not need to be the same width as the input. AMDGPU, NVPTX, and Hexagon all have patterns working around the types matching. GlobalISel defines these as being different type indexes.
  9. [libclang] Fix UninstallAbortingLLVMFatalErrorHandler test
  10. AMDGPU: Add immarg to llvm.amdgcn.init.exec.from.input As far as I can tell this has to be a constant.
  11. LiveIntervals: Remove assertion This testcase is invalid, and caught by the verifier. For the verifier to catch it, the live interval computation needs to complete. Remove the assert so the verifier catches this, which is less confusing. In this testcase there is an undefined use of a subregister, and lanes which aren't used or defined. An equivalent testcase with the super-register shrunk to have no untouched lanes already hit this verifier error.
  12. AMDGPU: Inline constant when materalizing FI with add on gfx9 This was relying on the SGPR usable for the carry out clobber to also be used for the input. There was no carry out on gfx9. With no carry out clobber to worry about, so the literal can just be directly used with a VOP2 add.
  13. [Test] Restructure check lines to show differences between modes more clearly With the landing of the previous patch (in particular D66318) there are a lot fewer diffs now. I added an experimental O0 line, and updated all the tests to group experimental and non-experimental O0/O3 together. Skimming the remaining diffs, there's only a few which are obviously incorrect. There's a large number which are questionable, so more todo.
  14. Rename nonvolatile_load/store to simple_load/store [NFC] Implement the TODO from D66318.
  15. [AArch64][GlobalISel] Support tail calling with swiftself parameters Swiftself uses a callee-saved register. We can tail call when the register used in the caller and callee is the same. This behaviour is equivalent to that in `TargetLowering::parametersInCSRMatch`. Update call-translator-tail-call.ll to verify that we can do this. When we support inline assembly, we can write a check similar to the one in the general swiftself.ll. For now, we need to verify that we get the correct COPY instruction after call lowering. Differential Revision: https://reviews.llvm.org/D67511
  16. [libclang] Expose abort()-ing LLVM fatal error handler Differential Revision: https://reviews.llvm.org/D66775
  17. [SDAG] Update generic code to conservatively check for isAtomic in addition to isVolatile This is the first sweep of generic code to add isAtomic bailouts where appropriate. The intention here is to have the switch from AtomicSDNode to LoadSDNode/StoreSDNode be close to NFC; that is, I'm not looking to allow additional optimizations at this time. That will come later. See D66309 for context. Differential Revision: https://reviews.llvm.org/D66318
  18. Add -Wpoison-system-directories warning When using clang as a cross-compiler, we should not use system headers to do the compilation. This CL adds support of a new warning flag -Wpoison-system-directories which emits warnings if --sysroot is set and headers from common host system location are used. By default the warning is disabled. The intention of the warning is to catch bad includes which are usually generated by third party build system not targeting cross-compilation. Such cases happen in Chrome OS when someone imports a new package or upgrade one to a newer version from upstream. Patch by: denik (Denis Nikitin)
Revision 371806 by shiva:
[RISCV] Support stack offset exceed 32-bit for RV64

Differential Revision: https://reviews.llvm.org/D61884
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVFrameLowering.cppllvm.src/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cppllvm.src/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.hllvm.src/lib/Target/RISCV/RISCVInstrInfo.h
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cppllvm.src/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was added/llvm/trunk/test/CodeGen/RISCV/rv64-large-stack.llllvm.src/test/CodeGen/RISCV/rv64-large-stack.ll
The file was modified/llvm/trunk/test/CodeGen/RISCV/stack-realignment.llllvm.src/test/CodeGen/RISCV/stack-realignment.ll
Revision 371805 by rsmith:
For PR17164: split -fno-lax-vector-conversion into three different
levels:

-- none: no lax vector conversions [new GCC default]
-- integer: only conversions between integer vectors [old GCC default]
-- all: all conversions between same-size vectors [Clang default]

For now, Clang still defaults to "all" mode, but per my proposal on
cfe-dev (2019-04-10) the default will be changed to "integer" as soon as
that doesn't break lots of testcases. (Eventually I'd like to change the
default to "none" to match GCC and general sanity.)

Following GCC's behavior, the driver flag -flax-vector-conversions is
translated to -flax-vector-conversions=integer.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/LangOptions.defclang.src/include/clang/Basic/LangOptions.def
The file was modified/cfe/trunk/include/clang/Basic/LangOptions.hclang.src/include/clang/Basic/LangOptions.h
The file was modified/cfe/trunk/include/clang/Driver/Options.tdclang.src/include/clang/Driver/Options.td
The file was modified/cfe/trunk/lib/Driver/ToolChains/Clang.cppclang.src/lib/Driver/ToolChains/Clang.cpp
The file was modified/cfe/trunk/lib/Frontend/CompilerInvocation.cppclang.src/lib/Frontend/CompilerInvocation.cpp
The file was modified/cfe/trunk/lib/Sema/SemaExpr.cppclang.src/lib/Sema/SemaExpr.cpp
The file was modified/cfe/trunk/test/CodeGen/builtins-systemz-vector.cclang.src/test/CodeGen/builtins-systemz-vector.c
The file was modified/cfe/trunk/test/CodeGen/builtins-systemz-vector2.cclang.src/test/CodeGen/builtins-systemz-vector2.c
The file was modified/cfe/trunk/test/CodeGen/builtins-systemz-vector3.cclang.src/test/CodeGen/builtins-systemz-vector3.c
The file was modified/cfe/trunk/test/CodeGen/builtins-systemz-zvector-error.cclang.src/test/CodeGen/builtins-systemz-zvector-error.c
The file was modified/cfe/trunk/test/CodeGen/builtins-systemz-zvector.cclang.src/test/CodeGen/builtins-systemz-zvector.c
The file was modified/cfe/trunk/test/CodeGen/builtins-systemz-zvector2-error.cclang.src/test/CodeGen/builtins-systemz-zvector2-error.c
The file was modified/cfe/trunk/test/CodeGen/builtins-systemz-zvector2.cclang.src/test/CodeGen/builtins-systemz-zvector2.c
The file was modified/cfe/trunk/test/CodeGen/builtins-systemz-zvector3-error.cclang.src/test/CodeGen/builtins-systemz-zvector3-error.c
The file was modified/cfe/trunk/test/CodeGen/builtins-systemz-zvector3.cclang.src/test/CodeGen/builtins-systemz-zvector3.c
The file was modified/cfe/trunk/test/CodeGen/builtins-wasm.cclang.src/test/CodeGen/builtins-wasm.c
The file was modified/cfe/trunk/test/CodeGenCXX/builtins-systemz-zvector.cppclang.src/test/CodeGenCXX/builtins-systemz-zvector.cpp
The file was modified/cfe/trunk/test/Headers/altivec-header.cclang.src/test/Headers/altivec-header.c
The file was modified/cfe/trunk/test/Headers/arm-neon-header.cclang.src/test/Headers/arm-neon-header.c
The file was modified/cfe/trunk/test/Headers/x86-intrinsics-headers-clean.cppclang.src/test/Headers/x86-intrinsics-headers-clean.cpp
The file was modified/cfe/trunk/test/Headers/x86-intrinsics-headers.cclang.src/test/Headers/x86-intrinsics-headers.c
The file was modified/cfe/trunk/test/Headers/x86intrin-2.cclang.src/test/Headers/x86intrin-2.c
The file was modified/cfe/trunk/test/Headers/x86intrin.cclang.src/test/Headers/x86intrin.c
The file was modified/cfe/trunk/test/Sema/ext_vector_casts.cclang.src/test/Sema/ext_vector_casts.c
The file was modified/cfe/trunk/test/Sema/typedef-retain.cclang.src/test/Sema/typedef-retain.c
The file was modified/cfe/trunk/test/Sema/zvector.cclang.src/test/Sema/zvector.c
The file was modified/cfe/trunk/test/Sema/zvector2.cclang.src/test/Sema/zvector2.c
The file was modified/cfe/trunk/test/SemaCXX/altivec.cppclang.src/test/SemaCXX/altivec.cpp
The file was modified/cfe/trunk/test/SemaCXX/vector-no-lax.cppclang.src/test/SemaCXX/vector-no-lax.cpp
The file was modified/cfe/trunk/test/SemaCXX/vector.cppclang.src/test/SemaCXX/vector.cpp
Revision 371803 by arsenm:
AMDGPU/GlobalISel: Legalize G_FFLOOR
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
Revision 371802 by timshen:
Temporarily revert r371640 "LiveIntervals: Split live intervals on multiple dead defs".

It reveals a miscompile on Hexagon. See PR43302 for details.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/LiveIntervals.cppllvm.src/lib/CodeGen/LiveIntervals.cpp
The file was removed/llvm/trunk/test/CodeGen/AMDGPU/live-intervals-multiple-dead-defs.mirllvm.src/test/CodeGen/AMDGPU/live-intervals-multiple-dead-defs.mir
Revision 371800 by arsenm:
AMDGPU/GlobalISel: Legalize G_FMAD

Unlike SelectionDAG, treat this as a normally legalizable operation.
In SelectionDAG this is supposed to only ever formed if it's legal,
but I've found that to be restricting. For AMDGPU this is contextually
legal depending on whether denormal flushing is allowed in the use
function.

Technically we currently treat the denormal mode as a subtarget
feature, so custom lowering could be avoided. However I consider this
to be a defect, and this should be contextually dependent on the
controllable rounding mode of the parent function.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerHelper.hllvm.src/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.hllvm.src/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cppllvm.src/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.hllvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
Revision 371799 by manojgupta:
Revert r371785.

r371785 is causing fails on clang-hexagon-elf buildbots.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.tdclang.src/include/clang/Basic/DiagnosticCommonKinds.td
The file was modified/cfe/trunk/lib/Frontend/InitHeaderSearch.cppclang.src/lib/Frontend/InitHeaderSearch.cpp
The file was removed/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_treeclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree
The file was removed/cfe/trunk/test/Frontend/warning-poison-system-directories.cclang.src/test/Frontend/warning-poison-system-directories.c
Revision 371798 by arsenm:
AMDGPU/GlobalISel: Select G_CTPOP
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.tdllvm.src/lib/Target/AMDGPU/SIInstrInfo.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstructions.tdllvm.src/lib/Target/AMDGPU/SIInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.tdllvm.src/lib/Target/AMDGPU/SOPInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.tdllvm.src/lib/Target/AMDGPU/VOP2Instructions.td
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
Revision 371797 by arsenm:
DAG/GlobalISel: Correct type profile of bitcount ops

The result integer does not need to be the same width as the input.
AMDGPU, NVPTX, and Hexagon all have patterns working around the types
matching. GlobalISel defines these as being different type indexes.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Target/TargetSelectionDAG.tdllvm.src/include/llvm/Target/TargetSelectionDAG.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstructions.tdllvm.src/lib/Target/AMDGPU/SIInstructions.td
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.tdllvm.src/lib/Target/Hexagon/HexagonPatterns.td
The file was modified/llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.tdllvm.src/lib/Target/NVPTX/NVPTXInstrInfo.td
The file was modified/llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.tdllvm.src/lib/Target/Sparc/SparcInstr64Bit.td
The file was modified/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.tdllvm.src/lib/Target/Sparc/SparcInstrInfo.td
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.tdllvm.src/lib/Target/SystemZ/SystemZInstrInfo.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.tdllvm.src/lib/Target/X86/X86InstrAVX512.td
Revision 371794 by Jan Korous:
[libclang] Fix UninstallAbortingLLVMFatalErrorHandler test
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/unittests/libclang/CrashTests/LibclangCrashTest.cppclang.src/unittests/libclang/CrashTests/LibclangCrashTest.cpp
Revision 371793 by arsenm:
AMDGPU: Add immarg to llvm.amdgcn.init.exec.from.input

As far as I can tell this has to be a constant.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.tdllvm.src/include/llvm/IR/IntrinsicsAMDGPU.td
Revision 371792 by arsenm:
LiveIntervals: Remove assertion

This testcase is invalid, and caught by the verifier. For the verifier
to catch it, the live interval computation needs to complete. Remove
the assert so the verifier catches this, which is less confusing.

In this testcase there is an undefined use of a subregister, and lanes
which aren't used or defined. An equivalent testcase with the
super-register shrunk to have no untouched lanes already hit this
verifier error.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/LiveInterval.cppllvm.src/lib/CodeGen/LiveInterval.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mirllvm.src/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
Revision 371791 by arsenm:
AMDGPU: Inline constant when materalizing FI with add on gfx9

This was relying on the SGPR usable for the carry out clobber to also
be used for the input. There was no carry out on gfx9. With no carry
out clobber to worry about, so the literal can just be directly used
with a VOP2 add.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cppllvm.src/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cppllvm.src/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.llllvm.src/test/CodeGen/AMDGPU/frame-index-elimination.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mirllvm.src/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
Revision 371790 by reames:
[Test] Restructure check lines to show differences between modes more clearly

With the landing of the previous patch (in particular D66318) there are a lot fewer diffs now.  I added an experimental O0 line, and updated all the tests to group experimental and non-experimental O0/O3 together.

Skimming the remaining diffs, there's only a few which are obviously incorrect.  There's a large number which are questionable, so more todo.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-unordered.llllvm.src/test/CodeGen/X86/atomic-unordered.ll
Revision 371789 by reames:
Rename nonvolatile_load/store to simple_load/store [NFC]

Implement the TODO from D66318.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Target/TargetSelectionDAG.tdllvm.src/include/llvm/Target/TargetSelectionDAG.td
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.tdllvm.src/lib/Target/SystemZ/SystemZInstrFP.td
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.tdllvm.src/lib/Target/SystemZ/SystemZInstrInfo.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.tdllvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrCompiler.tdllvm.src/lib/Target/X86/X86InstrCompiler.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrMMX.tdllvm.src/lib/Target/X86/X86InstrMMX.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.tdllvm.src/lib/Target/X86/X86InstrSSE.td
Revision 371788 by paquette:
[AArch64][GlobalISel] Support tail calling with swiftself parameters

Swiftself uses a callee-saved register. We can tail call when the register used
in the caller and callee is the same.

This behaviour is equivalent to that in `TargetLowering::parametersInCSRMatch`.

Update call-translator-tail-call.ll to verify that we can do this. When we
support inline assembly, we can write a check similar to the one in the
general swiftself.ll. For now, we need to verify that we get the correct COPY
instruction after call lowering.

Differential Revision: https://reviews.llvm.org/D67511
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cppllvm.src/lib/Target/AArch64/AArch64CallLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.llllvm.src/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
Revision 371787 by Jan Korous:
[libclang] Expose abort()-ing LLVM fatal error handler

Differential Revision: https://reviews.llvm.org/D66775
Change TypePath in RepositoryPath in Workspace
The file was added/cfe/trunk/include/clang-c/FatalErrorHandler.hclang.src/include/clang-c/FatalErrorHandler.h
The file was modified/cfe/trunk/tools/libclang/CIndex.cppclang.src/tools/libclang/CIndex.cpp
The file was modified/cfe/trunk/tools/libclang/CMakeLists.txtclang.src/tools/libclang/CMakeLists.txt
The file was added/cfe/trunk/tools/libclang/FatalErrorHandler.cppclang.src/tools/libclang/FatalErrorHandler.cpp
The file was modified/cfe/trunk/tools/libclang/libclang.exportsclang.src/tools/libclang/libclang.exports
The file was modified/cfe/trunk/unittests/libclang/CMakeLists.txtclang.src/unittests/libclang/CMakeLists.txt
The file was added/cfe/trunk/unittests/libclang/CrashTestsclang.src/unittests/libclang/CrashTests
The file was added/cfe/trunk/unittests/libclang/CrashTests/CMakeLists.txtclang.src/unittests/libclang/CrashTests/CMakeLists.txt
The file was added/cfe/trunk/unittests/libclang/CrashTests/LibclangCrashTest.cppclang.src/unittests/libclang/CrashTests/LibclangCrashTest.cpp
Revision 371786 by reames:
[SDAG] Update generic code to conservatively check for isAtomic in addition to isVolatile

This is the first sweep of generic code to add isAtomic bailouts where appropriate. The intention here is to have the switch from AtomicSDNode to LoadSDNode/StoreSDNode be close to NFC; that is, I'm not looking to allow additional optimizations at this time. That will come later.  See D66309 for context.

Differential Revision: https://reviews.llvm.org/D66318
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Target/TargetSelectionDAG.tdllvm.src/include/llvm/Target/TargetSelectionDAG.td
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cppllvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cppllvm.src/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cppllvm.src/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cppllvm.src/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-unordered.llllvm.src/test/CodeGen/X86/atomic-unordered.ll
Revision 371785 by manojgupta:
Add -Wpoison-system-directories warning

When using clang as a cross-compiler, we should not use system
headers to do the compilation.
This CL adds support of a new warning flag -Wpoison-system-directories which
emits warnings if --sysroot is set and headers from common host system location
are used.
By default the warning is disabled.

The intention of the warning is to catch bad includes which are usually
generated by third party build system not targeting cross-compilation.
Such cases happen in Chrome OS when someone imports a new package or upgrade
one to a newer version from upstream.

Patch by: denik (Denis Nikitin)
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.tdclang.src/include/clang/Basic/DiagnosticCommonKinds.td
The file was modified/cfe/trunk/lib/Frontend/InitHeaderSearch.cppclang.src/lib/Frontend/InitHeaderSearch.cpp
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_treeclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/libclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/lib
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/lib/.keepclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/lib/.keep
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usrclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/includeclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/include
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/include/c++clang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/include/c++
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/include/c++/.keepclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/include/c++/.keep
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/libclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/lib
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/lib/gccclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/lib/gcc
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/lib/gcc/.keepclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/lib/gcc/.keep
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/localclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/includeclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/include
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/include/.keepclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/include/.keep
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/libclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/lib
The file was added/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/lib/.keepclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/lib/.keep
The file was added/cfe/trunk/test/Frontend/warning-poison-system-directories.cclang.src/test/Frontend/warning-poison-system-directories.c