FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [ELF] Fix lld build on Windows/MinGW (details)
  2. [PowerPC] Implementing overflow version for XO-Form instructions (details)
  3. [PowerPC] Fix crash in peephole optimization (details)
Commit 0a64fe568090a6e298669d901cdff7b356194aa5 by tstellar
[ELF] Fix lld build on Windows/MinGW
The patch in https://reviews.llvm.org/D64077 causes a build failure
because both the Defined and SharedSymbol classes are bigger than 80
bytes on MinGW 8.
This patch fixes this build failure by changing the type of the
bitfields. It is a similar change to the bitfield changes in
https://reviews.llvm.org/D64238, but instead of changing to bool I
decided to use uint8_t because one of the bitfields takes up two bits
instead of one.
Note: the patch is slightly different from the one reviewed in
Phabricator, but it is a trivial change to align it with LLVM master
instead of LLVM 9. Also, it passes all lld tests.
Differential Revision: https://reviews.llvm.org/D70266
(cherry picked from commit 57776f71fa32a5b170a9ce82cb2c2da0a207908c)
The file was modifiedlld/ELF/Symbols.h
Commit ed3f33f9dca7a036166b4daf0cbb98b0e129879a by tstellar
[PowerPC] Implementing overflow version for XO-Form instructions
The Overflow version of XO-Form instruction uses the SO, OV and OV32
special registers.
This changes modifies existing multiclasses and instruction definitions
to allow for the use of the XER register to record the various types if
overflow from possible add, subtract and multiply instructions. It then
modifies the existing instructions as to use these multiclasses as
needed.
Patch By: Kamau Bridgeman
Differential Revision: https://reviews.llvm.org/D66902
(cherry picked from commit fdf3d1766bbabb48a397fae646facbe2690313f6)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
The file was modifiedllvm/lib/Target/PowerPC/P9InstrResources.td
The file was modifiedllvm/test/MC/PowerPC/invalid-instructions-spellcheck.s
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding.s
Commit 52ac91476dcffc5ecb3a6ff0e63b27f8a13edd4a by tstellar
[PowerPC] Fix crash in peephole optimization
When converting reg+reg shifts to reg+imm rotates, we neglect to
consider the CodeGenOnly versions of the 32-bit shift mnemonics. This
means we produce a rotate with missing operands which causes a crash.
Committing this fix without review since it is non-controversial that
the list of mnemonics to consider should include the 64-bit aliases for
the exact mnemonics.
Fixes PR44183.
(cherry picked from commit 241cbf201a6f4b7658697e3c76fc6e741d049a01)
The file was addedllvm/test/CodeGen/PowerPC/pr44183.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp