FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [gn build] Port 96d4ccf00c8 (details)
  2. [AST][RecoveryExpr] Populate error-bit from Type to Expr. (details)
  3. [ARM][BFloat] Legalize bf16 type even without fullfp16. (details)
  4. [AMDGPU] Enable compare operations to be selected by divergence (details)
  5. [DSE,MSSA] Precommit small test changes for D72631. (details)
  6. [lldb] fix typo in docs: withing -> within (details)
  7. [ARM] Improve diagnostics message when Neon is unsupported (details)
  8. [AArch64][SVE] Add bfloat16 support to load intrinsics (details)
Commit 9df3e6e24d610b36e125affb341cecffb63db46e by llvmgnsyncbot
[gn build] Port 96d4ccf00c8
The file was modifiedllvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
Commit bfec030e69afc73b29aa1b66902ae802a448fc19 by hokein.wu
[AST][RecoveryExpr] Populate error-bit from Type to Expr.

Summary: Looks like this is a fallout when we introduce the error-bit in Type.

Reviewers: sammccall

Reviewed By: sammccall

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D82099
The file was modifiedclang/test/SemaCXX/invalid-template-base-specifier.cpp
The file was modifiedclang/include/clang/AST/DependenceFlags.h
Commit b769eb02b526e3966847351e15d283514c2ec767 by simon.tatham
[ARM][BFloat] Legalize bf16 type even without fullfp16.

Summary:
This change permits scalar bfloats to be loaded, stored, moved and
used as function call arguments and return values, whenever the bf16
feature is supported by the subtarget.

Previously that was only supported in the presence of the fullfp16
feature, because the code generation strategy depended on instructions
from that extension. This change adds alternative code generation
strategies so that those operations can be done even without fullfp16.

The strategy for loads and stores is to replace VLDRH/VSTRH with
integer LDRH/STRH plus a move between register classes. I've written
isel patterns for those, conditional on //not// having the fullfp16
feature (so that in the fullfp16 case, the existing patterns will
still be used).

For function arguments and returns, instead of writing isel patterns
to match `VMOVhr` and `VMOVrh`, I've avoided generating those SDNodes
in the first place, by factoring out the code that constructs them
into helper functions `MoveToHPR` and `MoveFromHPR` which have a
fallback for non-fullfp16 subtargets.

The current output code is not especially pretty: in the new test file
you can see unnecessary store/load pairs implementing no-op bitcasts,
and lots of pointless moves back and forth between FP registers and
GPRs. But it at least works, which is an improvement on the previous
situation.

Reviewers: dmgreen, SjoerdMeijer, stuij, chill, miyuki, labrinea

Reviewed By: dmgreen, labrinea

Subscribers: labrinea, kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82372
The file was modifiedllvm/lib/Target/ARM/ARMInstrVFP.td
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMPredicates.td
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was addedllvm/test/CodeGen/ARM/arm-bf16-pcs.ll
Commit 521ac0b5cea02f629d035f807460affbb65ae7ad by alex-t
[AMDGPU] Enable compare operations to be selected by divergence

Summary: Details: This patch enables SETCC to be selected to S_CMP_* if uniform and V_CMP_* if divergent.

Reviewers: rampitec, arsenm

Reviewed By: rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82194
The file was modifiedllvm/test/CodeGen/AMDGPU/addrspacecast.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/setcc-opt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vselect.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/udiv64.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sdiv64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shift-i128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/loop_break.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sad.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/selectcc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/min.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-cfg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/srem64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fshl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sign_extend.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.mulo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/urem64.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/select-vectors.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/or.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/udivrem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/setcc64.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/zero_extend.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/v_cndmask.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/setcc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/selectcc-opt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/saddo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/select-opt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-select-ptr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sint_to_fp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ctlz.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/icmp64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uint_to_fp.ll
Commit 7b72cb47e6cd9d67f7d4b5ef4d66db6c516f80a9 by flo
[DSE,MSSA] Precommit small test changes for D72631.
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memintrinsics.ll
Commit 4bfa43809fe6780159a4980cf601c504cbec6f32 by kkleine
[lldb] fix typo in docs: withing -> within
The file was modifiedlldb/docs/resources/caveats.rst
Commit 1b090db0df47f3ebf6acab0316180267e6b96f43 by victor.campos
[ARM] Improve diagnostics message when Neon is unsupported

Summary:
Whenever Neon is not supported, a generic message is printed:

  error: "NEON support not enabled"

Followed by a series of other error messages that are not useful once
the first one is printed.

This patch gives a more precise message in the case where Neon is
unsupported because an invalid float ABI was specified: the soft float
ABI.

  error: "NEON intrinsics not available with the soft-float ABI. Please
  use -mfloat-abi=softfp or -mfloat-abi=hard"

This message is the same one that GCC gives, so it is also making their
diagnostics more compatible with each other.

Also, by rearranging preprocessor directives, these "unsupported" error
messages are now the only ones printed out, which is also GCC's
behaviour.

Differential Revision: https://reviews.llvm.org/D81847
The file was modifiedclang/utils/TableGen/NeonEmitter.cpp
Commit 3d6cab271c7cecf105b77834d837ccd4406700d7 by kerry.mclaughlin
[AArch64][SVE] Add bfloat16 support to load intrinsics

Summary:
Bfloat16 support added for the following intrinsics:
- LD1
- LD1RQ
- LDNT1
- LDNF1
- LDFF1

Reviewers: sdesmalen, c-rhodes, efriedma, stuij, fpetrogalli, david-arm

Reviewed By: fpetrogalli

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D82298
The file was addedclang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1-bfloat.c
The file was addedclang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1rq-bfloat.c
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-ld1-addressing-mode-reg-imm.ll
The file was modifiedclang/include/clang/Basic/arm_sve.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-ld1-addressing-mode-reg-reg.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
The file was addedclang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnt1-bfloat.c
The file was addedclang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1-bfloat.c
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-loads-ff.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-ld1.ll
The file was addedclang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c