FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [clang driver] Move default module cache from system temporary directory (details)
  2. Triple.h - reduce Twine.h include to forward declarations. NFC. (details)
  3. Improve LegacyPassManager API to correctly report modified status (details)
  4. Fix implicit Twine.h include dependency. (details)
  5. [builtins] Improve compatibility with 16 bit targets (details)
  6. [MSP430] Update register names (details)
  7. [AArch64][SVE] Only support sizeless bfloat types if supported by subtarget (details)
  8. Fix implicit include dependencies on SmallVector.h. (details)
  9. [MLIR][Affine-loop-fusion] Fix a bug in affine-loop-fusion pass when there are non-affine operations (details)
  10. [mlir-tblgen] Use fully qualified names in generated code files (details)
  11. Add explicit Twine.h include to try and fix ICE on clang-ppc64be-linux (details)
  12. [lldb] Re-add X-Fail for Windows to TestDollarInVariable (details)
  13. [mlir] support returning unranked memrefs (details)
  14. [mlir] Avoid creating local OpBuilders in Standard-to-LLVM conversion (details)
  15. [mlir] fix off-by-one error in collapseParallelLoops (details)
  16. [MLIR][SPIRV] Add support for OpCopyMemory. (details)
  17. Revert rGf0bab7875e78e01c149d12302dcc4b6d4c43e25c - "Triple.h - reduce Twine.h include to forward declarations. NFC." (details)
  18. Fix pass return status for loop extractor (details)
  19. [AArch64][SVE] Remove asserts from AArch64ISelLowering for bfloat16 types (details)
  20. [CodeComplete] Add code completion for using alias. (details)
  21. [mlir][spirv] Add RewriteInserts pass. (details)
  22. AMDGPU/GlobalISel: Uncomment some fixed tests (details)
  23. AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI (details)
  24. AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI (details)
  25. [Alignment][NFC] Migrate TTI::isLegalToVectorize{Load,Store}Chain to Align (details)
Commit bb26838ceffb5feaa18186f55f7525a08084899e by dave
[clang driver] Move default module cache from system temporary directory

1) Shared writable directories like /tmp are a security problem.
2) Systems provide dedicated cache directories these days anyway.
3) This also refines LLVM's cache_directory() on Darwin platforms to use
   the Darwin per-user cache directory.

Reviewers: compnerd, aprantl, jakehehrlich, espindola, respindola, ilya-biryukov, pcc, sammccall

Reviewed By: compnerd, sammccall

Subscribers: hiraditya, llvm-commits, cfe-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D82362
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/include/clang/Driver/Driver.h
The file was modifiedclang/unittests/Driver/ModuleCacheTest.cpp
The file was modifiedclang/test/Driver/modules-cache-path.m
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedllvm/lib/Support/Unix/Path.inc
Commit f0bab7875e78e01c149d12302dcc4b6d4c43e25c by llvm-dev
Triple.h - reduce Twine.h include to forward declarations. NFC.

Move include down to a number of other files that had an implicit dependency on the Twine class.
The file was modifiedllvm/lib/Support/Triple.cpp
The file was modifiedllvm/unittests/Frontend/OpenMPContextTest.cpp
The file was modifiedllvm/include/llvm/Support/TargetRegistry.h
The file was modifiedclang/lib/Basic/Targets/Mips.h
The file was modifiedllvm/include/llvm/ADT/Triple.h
The file was modifiedllvm/lib/MC/MCSectionELF.cpp
The file was modifiedllvm/unittests/Support/ThreadPool.cpp
The file was modifiedllvm/unittests/ADT/TripleTest.cpp
The file was modifiedclang/lib/Basic/IdentifierTable.cpp
Commit 55fe7b79bb7fab49af3720840224c0720bdb03c6 by sguelton
Improve LegacyPassManager API to correctly report modified status

When calling on-the-fly passes from the legacy pass manager, the modification
status is not reported, which is a problem in case we depend on an acutal
transformation pass, and not only analyse.

Update the Legacy PM API to optionally report the changed status, assert if a
change is detected but this change is lost.

Related to https://reviews.llvm.org/D80916

Differential Revision: https://reviews.llvm.org/D81236
The file was modifiedllvm/include/llvm/IR/LegacyPassManagers.h
The file was modifiedllvm/include/llvm/Pass.h
The file was modifiedllvm/include/llvm/PassAnalysisSupport.h
The file was modifiedllvm/lib/IR/LegacyPassManager.cpp
Commit 754f3c4af4b8526d7576c8e92959ad10d40b6e2e by llvm-dev
Fix implicit Twine.h include dependency.
The file was modifiedlldb/tools/intel-features/intel-mpx/cli-wrapper-mpxtable.cpp
Commit a4e8f7fe3f38085c0fdd6e34e870f8e9c6c72861 by anton
[builtins] Improve compatibility with 16 bit targets

Some parts of existing codebase assume the default `int` type to be (at least) 32 bit wide. On 16 bit targets such as MSP430 this may cause Undefined Behavior or results being defined but incorrect.

Differential Revision: https://reviews.llvm.org/D81408
The file was modifiedcompiler-rt/lib/builtins/fp_lib.h
The file was modifiedcompiler-rt/lib/builtins/floatdidf.c
The file was modifiedcompiler-rt/lib/builtins/floatundidf.c
Commit cb56fa2196c5d80ce72e8e8f6ee2a7ac80acca77 by anton
[MSP430] Update register names

When writing a unit test on replacing standard epilogue sequences with `BR __mspabi_func_epilog_<N>`, by manually asm-clobbering `rN` - `r10` for N = 4..10, everything worked well except for seeming inability to clobber r4.

The problem was that MSP430 code generator of LLVM used an obsolete name FP for that register. Things were worse because when `llc` read an unknown register name, it silently ignored it.

That is, I cannot use `fp` register name from the C code because Clang does not accept it (exactly like GCC). But the accepted name `r4` is not recognised by `llc` (it can be used in listings passed to `llvm-mc` and even `fp` is replace to `r4` by `llvm-mc`). So I can specify any of `fp` or `r4` for the string literal of `asm(...)` but nothing in the clobber list.

This patch replaces `MSP430::FP` with `MSP430::R4` in the backend code (even [MSP430 EABI](http://www.ti.com/lit/an/slaa534/slaa534.pdf) doesn't mention FP as a register name). The R0 - R3 registers, on the other hand, are left as is in the backend code (after all, they have some special meaning on the ISA level). It is just ensured clang is renaming them as expected by the downstream tools. There is probably not much sense in **marking them clobbered** but rename them //just in case// for use at potentially different contexts.

Differential Revision: https://reviews.llvm.org/D82184
The file was modifiedllvm/test/CodeGen/MSP430/asm-clobbers.ll
The file was modifiedllvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
The file was modifiedllvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
The file was modifiedllvm/lib/Target/MSP430/MSP430RegisterInfo.td
The file was addedllvm/test/CodeGen/MSP430/inline-asm-register-names.ll
The file was modifiedllvm/lib/Target/MSP430/MSP430FrameLowering.cpp
The file was modifiedllvm/lib/Target/MSP430/MSP430ISelLowering.cpp
The file was addedclang/test/CodeGen/msp430-register-names.c
The file was modifiedclang/lib/Basic/Targets/MSP430.h
The file was modifiedllvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
Commit 4319c48fc7fd196864121db2066d3b3561577406 by cullen.rhodes
[AArch64][SVE] Only support sizeless bfloat types if supported by subtarget

Reviewers: sdesmalen, efriedma, kmclaughlin, fpetrogalli

Reviewed By: sdesmalen, fpetrogalli

Differential Revision: https://reviews.llvm.org/D82494
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 41eb63929183c0913886c407b925f1716234cf8e by simon.tatham
Fix implicit include dependencies on SmallVector.h.

Both `AArch64TargetParser.h` and `ARMTargetParser.h` refer to
`SmallVectorImpl` without directly including the header that defines
it, which works fine until nothing else happens to include it anyway.
The file was modifiedllvm/include/llvm/Support/ARMTargetParser.h
The file was modifiedllvm/include/llvm/Support/AArch64TargetParser.h
Commit 2b5d1776ffad2614756ef059d64b957c7731e7be by uday
[MLIR][Affine-loop-fusion] Fix a bug in affine-loop-fusion pass when there are non-affine operations

When there is a mix of affine load/store and non-affine operations (e.g. std.load, std.store),
affine-loop-fusion ignores the present of non-affine ops, thus changing the program semantics.

E.g. we have a program of three affine loops operating on the same memref in which one of them uses std.load and std.store, as follows.
```
affine.for
  affine.store %1
affine.for
  std.load %1
  std.store %1
affine.for
  affine.load %1
  affine.store %1
```
affine-loop-fusion will produce the following result which changed the program semantics:
```
affine.for
  std.load %1
  std.store %1
affine.for
  affine.store %1
  affine.load %1
  affine.store %1
```

This patch is to fix the above problem by checking non-affine users of the memref that are between the source and destination nodes of interest.

Differential Revision: https://reviews.llvm.org/D82158
The file was modifiedmlir/lib/Transforms/LoopFusion.cpp
The file was modifiedmlir/test/Transforms/loop-fusion.mlir
Commit 05b4ff0a4b1a822449e9bf98782b9d337e6f81cf by jean-michel.gorius
[mlir-tblgen] Use fully qualified names in generated code files

Using fully qualified names wherever possible avoids ambiguous class and function names. This is a follow-up to D82371.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D82471
The file was modifiedmlir/test/mlir-tblgen/op-operand.td
The file was modifiedmlir/test/mlir-tblgen/op-side-effects.td
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/test/mlir-tblgen/predicate.td
The file was modifiedmlir/lib/TableGen/OpClass.cpp
The file was modifiedmlir/tools/mlir-tblgen/EnumsGen.cpp
The file was modifiedmlir/test/mlir-tblgen/op-attribute.td
The file was modifiedmlir/test/mlir-tblgen/op-decl.td
The file was modifiedmlir/unittests/TableGen/EnumsGenTest.cpp
The file was modifiedmlir/test/mlir-tblgen/op-result.td
The file was modifiedmlir/tools/mlir-tblgen/StructsGen.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/tools/mlir-tblgen/RewriterGen.cpp
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/tools/mlir-tblgen/PassGen.cpp
The file was modifiedmlir/test/mlir-tblgen/op-interface.td
The file was modifiedmlir/tools/mlir-tblgen/OpInterfacesGen.cpp
Commit 6551b7a9d8870ff67c275607fe730795644f99e7 by llvm-dev
Add explicit Twine.h include to try and fix ICE on clang-ppc64be-linux
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
Commit bb91520e4fe89ad35bc89578601bf1c35bd9d2fc by Raphael Isemann
[lldb] Re-add X-Fail for Windows to TestDollarInVariable

This got removed by accident in 048d11de43be087fd2fa0c5e35f20486f6094c29 when
the test was rewritten as a non-inline test.
The file was modifiedlldb/test/API/commands/expression/dollar-in-variable/TestDollarInVariable.py
Commit 6323065fd6026de926b15bb609f4601e366a300c by zinenko
[mlir] support returning unranked memrefs

Initially, unranked memref descriptors in the LLVM dialect were designed only
to be passed into functions. An assertion was guarding against returning
unranked memrefs from functions in the standard-to-LLVM conversion. This is
insufficient for functions that wish to return an unranked memref such that the
caller does not know the rank in advance, and hence cannot allocate the
descriptor and pass it in as an argument.

Introduce a calling convention for returning unranked memref descriptors as
follows. An unranked memref descriptor always points to a ranked memref
descriptor stored on stack of the current function. When an unranked memref
descriptor is returned from a function, the ranked memref descriptor it points
to is copied to dynamically allocated memory, the ownership of which is
transferred to the caller. The caller is responsible for deallocating the
dynamically allocated memory and for copying the pointed-to ranked memref
descriptor onto its stack.

Provide default lowerings for std.return, std.call and std.indirect_call that
maintain the conversion defined above.

This convention is additionally exercised by a runtime test to guard against
memory errors.

Differential Revision: https://reviews.llvm.org/D82647
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/test/Conversion/StandardToLLVM/calling-convention.mlir
The file was modifiedmlir/docs/ConversionToLLVMDialect.md
The file was modifiedmlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h
The file was modifiedmlir/test/Dialect/LLVMIR/roundtrip.mlir
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
The file was modifiedmlir/test/mlir-cpu-runner/unranked_memref.mlir
The file was modifiedmlir/test/Target/llvmir-intrinsics.mlir
Commit 8304ab5799b4172462877ca7495115c659ec0be0 by zinenko
[mlir] Avoid creating local OpBuilders in Standard-to-LLVM conversion

Conversions of allocation-related operations in Standard-to-LLVM need
declarations of "malloc" and "free" (or equivalents). They use locally created
OpBuilders pointed at the module level to declare these functions if necessary.
This is poorly compatible with the pattern infrastructure that is unaware of
new operations being created. Update the insertion point of the main rewriter
instead.

Differential Revision: https://reviews.llvm.org/D82649
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
Commit 652a79659a89b3634f34c6cf94a0b18b25ea4419 by tobias.gysi
[mlir] fix off-by-one error in collapseParallelLoops

Summary: The patch fixes an off by one error in the method collapseParallelLoops. It ensures the same normalized bound is used for the computation of the division and the remainder.

Reviewers: herhut

Reviewed By: herhut

Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, stephenneuendorffer, Joonsoo, grosul1, Kayjukh, jurahul, msifontes

Tags: #mlir

Differential Revision: https://reviews.llvm.org/D82634
The file was modifiedmlir/test/Transforms/single-parallel-loop-collapsing.mlir
The file was modifiedmlir/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedmlir/test/Transforms/parallel-loop-collapsing.mlir
Commit d6485ed3a7701364650bffabcbc277733f37eaa7 by antiagainst
[MLIR][SPIRV] Add support for OpCopyMemory.

This patch add support for 'spv.CopyMemory'. The following changes are
introduced:
- 'CopyMemory' op is added to SPIRVOps.td.
- Custom parse and print methods are introduced.
- A few Roundtripping tests are added.

Differential Revision: https://reviews.llvm.org/D82384
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVBase.td
The file was modifiedmlir/test/Dialect/SPIRV/ops.mlir
The file was modifiedmlir/test/Dialect/SPIRV/Serialization/memory-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVOps.td
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVOps.cpp
Commit 0069824feab0af5ade571d975deb1efd893c2466 by llvm-dev
Revert rGf0bab7875e78e01c149d12302dcc4b6d4c43e25c - "Triple.h - reduce Twine.h include to forward declarations. NFC."

This causes ICEs on the clang-ppc64be buildbots and I've limited ability to triage the problem.
The file was modifiedclang/lib/Basic/IdentifierTable.cpp
The file was modifiedllvm/include/llvm/ADT/Triple.h
The file was modifiedllvm/lib/MC/MCSectionELF.cpp
The file was modifiedllvm/unittests/Frontend/OpenMPContextTest.cpp
The file was modifiedllvm/include/llvm/Support/TargetRegistry.h
The file was modifiedclang/lib/Basic/Targets/Mips.h
The file was modifiedllvm/unittests/Support/ThreadPool.cpp
The file was modifiedllvm/lib/Support/Triple.cpp
The file was modifiedllvm/unittests/ADT/TripleTest.cpp
Commit 44f06db43941749b631756ff13cf7e8f7b2903fe by sguelton
Fix pass return status for loop extractor

As loop extractor has a dependency on another pass (namely BreakCriticalEdges)
that may update the IR, use the getAnalysis version introduced in
55fe7b79bb7fab49af3720840224c0720bdb03c6 to carry that change.

Add an assert in getAnalysisID to make sure no other changed status is missed -
according to validation this was the only one.

Related to https://reviews.llvm.org/D80916

Differential Revision: https://reviews.llvm.org/D81236
The file was modifiedllvm/lib/Transforms/IPO/LoopExtractor.cpp
The file was modifiedllvm/include/llvm/PassAnalysisSupport.h
Commit 6b313f198c95218b953f2c992f702f178c61cd1d by kerry.mclaughlin
[AArch64][SVE] Remove asserts from AArch64ISelLowering for bfloat16 types

Remove the asserts in performLDNT1Combine & performST[NT]1Combine
to ensure we get a failure where the type is a bfloat16 and
hasBF16() is false, regardless of whether asserts are enabled.
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 5547a83c0b68a03a806d47782a4d3a6dc3b5d5f5 by kadircet
[CodeComplete] Add code completion for using alias.

Add code completion for using alias.

Patch By @lh123 !

Reviewers: kadircet

Differential Revision: https://reviews.llvm.org/D82535
The file was modifiedclang/test/CodeCompletion/ordinary-name-cxx11.cpp
The file was modifiedclang/test/CodeCompletion/ordinary-name.cpp
The file was modifiedclang/lib/Sema/SemaCodeComplete.cpp
Commit a2004c344bf0028313948e720da35da24bcbb7a9 by antiagainst
[mlir][spirv] Add RewriteInserts pass.

Add a pass to rewrite sequential chains of `spirv::CompositeInsert`
operations into `spirv::CompositeConstruct` operations.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D82198
The file was addedmlir/test/Dialect/SPIRV/Transforms/rewrite-inserts.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/Passes.td
The file was addedmlir/lib/Dialect/SPIRV/Transforms/RewriteInsertsPass.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/Transforms/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/SPIRV/Passes.h
Commit b1cfa64cb15a0e84c953491c557b088605dac015 by Matthew.Arsenault
AMDGPU/GlobalISel: Uncomment some fixed tests
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
Commit 54573528ae8b2391f8386c9c8611760936b457ee by Matthew.Arsenault
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI

I'm not sure we actually need to support this now, since I think
clover always explicitly uses amdgcn-mesa-mesa3d now, not the
ill-defined amdgcn-- behavior.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
Commit 431daedee4dcce0c096c400dbf8e64dfe7254fb6 by Matthew.Arsenault
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI

This had an extra attempt to align the pointer, which only did
anything with a base kernel argument offset which only clover used to
use.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
Commit 1507fc15064a253aad1fdfff147babf003a42dc8 by gchatelet
[Alignment][NFC] Migrate TTI::isLegalToVectorize{Load,Store}Chain to Align

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82653
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h