FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [X86] Use some preprocessor macros to reduce the very similar repeated code in getVPTESTMOpc. NFCI (details)
  2. split darwin-version-min-load-command.s into Arm64 subtest to avoid failures (details)
  3. [PPC][NFC] Replace TM with Subtarget->getTargetMachine() in preparation for GlobalISel. (details)
  4. [BasicAA] Replace -basicaa with -basic-aa in polly (details)
  5. [clangd] Run formatting operations asynchronously. (details)
  6. [mlir] Add support for defining Traits and Interfaces on Attributes/Types. (details)
  7. [mlir] Refactor InterfaceGen to support generating interfaces for Attributes and Types. (details)
  8. [mlir] Remove locking for dialect/operation registration. (details)
  9. [Docs][BasicAA] Rename -basicaa to -basic-aa in docs (details)
  10. [ModuloSchedule] Make PeelingModuloScheduleExpander inheritable. (details)
  11. [gn build] Update build for new OpenMP tablegen logic (details)
  12. Fix wrong title underline length (details)
  13. A constexpr virtual function is implicitly inline so should never be a (details)
  14. AMDGPU/GlobalISel: Remove some selection tests which should be invalid (details)
  15. GlobalISel: Disallow undef generic virtual register uses (details)
  16. [gn build] (semi-manually) port ce6153a5282 (details)
  17. [Sanitizers] Implement interceptors for msgsnd, msgrcv (details)
  18. [Docs][BasicAA] Rename some more basicaa -> basic-aa (details)
Commit 1df1186ab12d87f42f3e8c5bd7703520d5bf1f17 by craig.topper
[X86] Use some preprocessor macros to reduce the very similar repeated code in getVPTESTMOpc. NFCI

This function picks X86 opcode name based on type, masking,
and whether not a load or broadcast has been folded using multiple
switch statements. The contents of the switches mostly just vary in
a few characters in the instruction name. So use some macros to
build the instruction names to reduce the repetiveness.
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit c8f1d442d0858f66fd4128fde6f67eb5202fa2b1 by Alex Lorenz
split darwin-version-min-load-command.s into Arm64 subtest to avoid failures

Some buildbot configurations don't build the arm64 backend, so the test-cases
that need arm64 should go into the aarch64 subdirectory.
The file was addedllvm/test/MC/MachO/AArch64/arm-darwin-version-min-load-command.s
The file was modifiedllvm/test/MC/MachO/darwin-version-min-load-command.s
Commit 4c2c6c7cc1663ee123be806fa02ead0f175568bc by kbarton
[PPC][NFC] Replace TM with Subtarget->getTargetMachine() in preparation for GlobalISel.

There are two uses of TM (instance of TargetMachine) when checking options.
These will not work once we enable GlobalISel. This patch replaces those uses of
TM with Subtarget->getTargetMachine().
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
Commit b210c9899bddf4c0332f8295b3b71938299e4835 by aeubanks
[BasicAA] Replace -basicaa with -basic-aa in polly

Follow up to https://reviews.llvm.org/D82607.
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_assign_scalar_2.ll
The file was modifiedpolly/test/ScopDetect/simple_loop_with_param.ll
The file was modifiedpolly/test/DependenceInfo/reduction_dependences_equal_non_reduction_dependences.ll
The file was modifiedpolly/test/DependenceInfo/reduction_partially_escaping_intermediate_in_other_stmt.ll
The file was modifiedpolly/test/Isl/CodeGen/create-conditional-scop.ll
The file was modifiedpolly/test/ScopInfo/mod_ref_read_pointee_arguments.ll
The file was modifiedpolly/test/Isl/Ast/dependence_distance_multiple_constant.ll
The file was modifiedpolly/test/ScopInfo/memmove.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_call.ll
The file was modifiedpolly/test/DependenceInfo/reduction_multiple_reductions.ll
The file was modifiedpolly/test/Isl/CodeGen/partial_write_mapped_vector.ll
The file was modifiedpolly/test/ScopInfo/reduction_disabled_multiplicative.ll
The file was modifiedpolly/test/Isl/CodeGen/loop_with_condition_nested.ll
The file was modifiedpolly/test/DeadCodeElimination/chained_iterations_2.ll
The file was modifiedpolly/test/ScopInfo/inter_bb_scalar_dep.ll
The file was modifiedpolly/test/Isl/CodeGen/MemAccess/simple_stride_test.ll
The file was modifiedpolly/test/ScopInfo/licm_potential_store.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_cast.ll
The file was modifiedpolly/test/ScopDetect/intrinsics_1.ll
The file was modifiedpolly/test/ScopInfo/intra_bb_scalar_dep.ll
The file was modifiedpolly/test/Isl/CodeGen/run-time-condition.ll
The file was modifiedpolly/test/ScopInfo/reduction_multiple_loops_array_sum.ll
The file was modifiedpolly/test/ScopInfo/licm_reduction_nested.ll
The file was modifiedpolly/test/ScheduleOptimizer/prevectorization-without-tiling.ll
The file was modifiedpolly/test/ScopDetect/mod_ref_read_pointer.ll
The file was modifiedpolly/www/documentation/gpgpucodegen.html
The file was modifiedpolly/test/Isl/CodeGen/loop_with_condition.ll
The file was modifiedpolly/test/ScheduleOptimizer/2012-04-16-Trivially-vectorizable-loops.ll
The file was modifiedpolly/test/ScopDetectionDiagnostics/ReportMultipleNonAffineAccesses.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_ptr_ptr_ty.ll
The file was modifiedpolly/test/ScopInfo/licm_load.ll
The file was modifiedpolly/test/ScopInfo/reduction_escaping_intermediate_2.ll
The file was modifiedpolly/test/DependenceInfo/reduction_multiple_loops_array_sum_2.ll
The file was modifiedpolly/test/DependenceInfo/reduction_multiple_reductions_2.ll
The file was modifiedpolly/test/Isl/CodeGen/loop_with_condition_ineq.ll
The file was modifiedpolly/test/ScopInfo/intra_and_inter_bb_scalar_dep.ll
The file was modifiedpolly/test/Isl/CodeGen/loop_with_condition_2.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_call_2.ll
The file was modifiedpolly/test/ScopInfo/reduction_invalid_different_operators.ll
The file was modifiedpolly/test/ScopInfo/tempscop-printing.ll
The file was modifiedpolly/test/ScopInfo/licm_reduction.ll
The file was modifiedpolly/test/ScopInfo/isl_aff_out_of_bounds.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_assign_scalar.ll
The file was modifiedpolly/test/ScopDetect/intrinsics_2.ll
The file was modifiedpolly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_1.ll
The file was modifiedpolly/test/DependenceInfo/sequential_loops.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_two_stmts.ll
The file was modifiedpolly/test/ScopInfo/memcpy-raw-source.ll
The file was modifiedpolly/test/DependenceInfo/reduction_multiple_loops_array_sum.ll
The file was modifiedpolly/test/Isl/CodeGen/MemAccess/default_aligned_new_access_function.ll
The file was modifiedpolly/test/ScopDetect/simple_loop_with_param_2.ll
The file was modifiedpolly/test/Isl/CodeGen/intrinsics_lifetime.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_large_width.ll
The file was modifiedpolly/test/ScopInfo/loop_carry.ll
The file was modifiedpolly/test/Isl/Ast/reduction_different_reduction_clauses.ll
The file was modifiedpolly/docs/experiments/matmul/runall.sh
The file was modifiedpolly/test/DeadCodeElimination/dead_iteration_elimination.ll
The file was modifiedpolly/test/ScopInfo/mod_ref_read_pointer.ll
The file was modifiedpolly/test/DeadCodeElimination/computeout.ll
The file was modifiedpolly/test/DependenceInfo/reduction_multiple_loops_array_sum_3.ll
The file was modifiedpolly/test/DeadCodeElimination/null_schedule.ll
The file was modifiedpolly/test/ScopInfo/NonAffine/non_affine_parametric_loop.ll
The file was modifiedpolly/test/ScopDetect/non-affine-loop-condition-dependent-access.ll
The file was modifiedpolly/test/Isl/CodeGen/intrinsics_misc.ll
The file was modifiedpolly/test/ScopInfo/memcpy.ll
The file was modifiedpolly/test/DeadCodeElimination/chained_iterations.ll
The file was modifiedpolly/test/ScopInfo/reduction_multiple_loops_array_sum_1.ll
The file was modifiedpolly/docs/HowToManuallyUseTheIndividualPiecesOfPolly.rst
The file was modifiedpolly/test/Isl/Ast/dependence_distance_varying_multiple.ll
The file was modifiedpolly/test/Isl/Ast/run-time-condition.ll
The file was modifiedpolly/test/Isl/CodeGen/invariant_load_hoist_alignment.ll
The file was modifiedpolly/test/ScopDetect/intrinsics_3.ll
The file was modifiedpolly/test/ScheduleOptimizer/prevectorization.ll
The file was modifiedpolly/test/ScheduleOptimizer/computeout.ll
The file was modifiedpolly/test/Isl/CodeGen/OpenMP/loop-body-references-outer-values-3.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_stride_x.ll
The file was modifiedpolly/test/DependenceInfo/reduction_two_reductions_different_rloops.ll
The file was modifiedpolly/test/Isl/CodeGen/reduction_2.ll
The file was modifiedpolly/test/ScopInfo/reduction_multiple_simple_binary.ll
The file was modifiedpolly/test/ScopInfo/scalar_to_array.ll
The file was modifiedpolly/test/ScopDetect/keep_going_expansion.ll
The file was modifiedpolly/test/ScopInfo/reduction_escaping_intermediate.ll
The file was modifiedpolly/test/DependenceInfo/do_pluto_matmult.ll
The file was modifiedpolly/test/ScopInfo/mod_ref_access_pointee_arguments.ll
The file was modifiedpolly/test/ScopInfo/mod_ref_read_pointers.ll
The file was modifiedpolly/test/Isl/Ast/single_loop_strip_mine.ll
The file was modifiedpolly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll
The file was modifiedpolly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_2.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_const.ll
The file was modifiedpolly/test/ScopInfo/licm_store.ll
The file was modifiedpolly/test/ScopInfo/assume_gep_bounds_2.ll
The file was modifiedpolly/test/Isl/Ast/reduction_dependences_equal_non_reduction_dependences.ll
Commit ffa63dde8e97a34b8914a151556551f74d4227e7 by sam.mccall
[clangd] Run formatting operations asynchronously.

Summary:
They don't need ASTs or anything, so they should still run immediately.

These were sync for historical reasons (they predate clangd having a pervasive
threading model). This worked ok as they were "cheap".
Aside for consistency, there are a couple of reasons to make them async:
- they do IO (finding .clang-format) so aren't trivially cheap
- having TUScheduler involved in running these tasks means we can use it as
   an injection point for configuration.
   (TUScheduler::run will need to learn about which file is being operated on,
   but that's an easy change).
- adding the config system adds more potential IO, too

Reviewers: kbobyrev

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D82642
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SyncAPI.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SyncAPI.h
The file was modifiedclang-tools-extra/clangd/unittests/ClangdTests.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
Commit 9fbb2de8e475cbb4ffa71280eb2ddc4922af05f6 by riddleriver
[mlir] Add support for defining Traits and Interfaces on Attributes/Types.

This revisions add mechanisms to Attribute/Type for attaching traits and interfaces. The mechanisms are modeled 1-1 after those for operations to keep the system consistent. AttrBase and TypeBase now accepts a trailing list of `Trait` types that will be attached to the object. These traits should inherit from AttributeTrait::TraitBase and TypeTrait::TraitBase respectively as necessary. A followup commit will refactor the interface gen mechanisms in ODS to support Attribute/Type interface generation and add tests for the mechanisms.

Differential Revision: https://reviews.llvm.org/D81883
The file was modifiedmlir/lib/IR/Attributes.cpp
The file was modifiedmlir/lib/IR/Types.cpp
The file was modifiedmlir/include/mlir/IR/Attributes.h
The file was modifiedmlir/include/mlir/IR/Types.h
The file was modifiedmlir/include/mlir/IR/StorageUniquerSupport.h
The file was modifiedmlir/lib/IR/MLIRContext.cpp
The file was modifiedmlir/include/mlir/IR/AttributeSupport.h
The file was modifiedmlir/include/mlir/IR/TypeSupport.h
The file was modifiedmlir/include/mlir/IR/Dialect.h
Commit 2e2cdd0a5230790300bdde7e5629fedef36d99b6 by riddleriver
[mlir] Refactor InterfaceGen to support generating interfaces for Attributes and Types.

This revision adds support to ODS for generating interfaces for attributes and types, in addition to operations. These interfaces can be specified using `AttrInterface` and `TypeInterface` in place of `OpInterface`. All of the features of `OpInterface` are supported except for the `verify` method, which does not have a matching representation in the Attribute/Type world. Generating these interface can be done using `gen-(attr|type)-interface-(defs|decls|docs)`.

Differential Revision: https://reviews.llvm.org/D81884
The file was addedmlir/lib/TableGen/Interfaces.cpp
The file was modifiedmlir/test/lib/Dialect/Test/CMakeLists.txt
The file was modifiedmlir/tools/mlir-tblgen/DialectGen.cpp
The file was modifiedmlir/test/lib/IR/CMakeLists.txt
The file was addedmlir/test/lib/IR/TestInterfaces.cpp
The file was modifiedmlir/lib/TableGen/CMakeLists.txt
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was removedmlir/include/mlir/TableGen/OpInterfaces.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
The file was modifiedmlir/include/mlir/TableGen/OpTrait.h
The file was modifiedmlir/docs/Interfaces.md
The file was modifiedmlir/lib/TableGen/OpTrait.cpp
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was modifiedmlir/include/mlir/IR/SymbolInterfaces.td
The file was modifiedmlir/include/mlir/Interfaces/CallInterfaces.td
The file was addedmlir/include/mlir/TableGen/Interfaces.h
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was addedmlir/test/mlir-tblgen/interfaces.mlir
The file was removedmlir/lib/TableGen/OpInterfaces.cpp
The file was modifiedmlir/docs/Traits.md
The file was modifiedmlir/test/lib/Dialect/Test/TestDialect.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpInterfacesGen.cpp
The file was modifiedmlir/include/mlir/Interfaces/SideEffectInterfaces.td
The file was addedmlir/test/lib/Dialect/Test/TestTypes.h
The file was addedmlir/test/lib/Dialect/Test/TestInterfaces.td
The file was modifiedmlir/include/mlir/Interfaces/ControlFlowInterfaces.td
The file was modifiedmlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp
The file was modifiedmlir/docs/OpDefinitions.md
Commit 5d699d18b32c0e0c27eceec026ed399e76e7e8ef by riddleriver
[mlir] Remove locking for dialect/operation registration.

Moving forward dialects should only be registered in a thread safe context. This matches the existing usage we have today, but it allows for removing quite a bit of expensive locking from the context.

This led to ~.5 a second compile time improvement when running one conversion pass on a very large .mlir file(hundreds of thousands of operations).

Differential Revision: https://reviews.llvm.org/D82595
The file was modifiedmlir/lib/IR/MLIRContext.cpp
The file was modifiedmlir/include/mlir/IR/Dialect.h
Commit 3dfe1440aecc285992b0f325b13c1b95468f0074 by aeubanks
[Docs][BasicAA] Rename -basicaa to -basic-aa in docs

Follow up to https://reviews.llvm.org/D82607.
The file was modifiedllvm/docs/Passes.rst
The file was modifiedllvm/docs/AliasAnalysis.rst
Commit 50ac7ce94f34c5f43b02185ae0c33e150e78b044 by hgreving
[ModuloSchedule] Make PeelingModuloScheduleExpander inheritable.

Basically a NFC, but allows subclasses access to the entire PeelingModuloScheduleExpander
class. We are doing this to allow backends, particularly one that are not necessarily
upstreamed, to inherit from PeelingModuloScheduleExpander and access its basic structures.

Renames Info into LoopInfo for consistency in PeelingModuloScheduleExpander.

Differential Revision: https://reviews.llvm.org/D82673
The file was modifiedllvm/lib/CodeGen/ModuloSchedule.cpp
The file was modifiedllvm/include/llvm/CodeGen/ModuloSchedule.h
Commit 926fab7c4fcd0a7cf00ca69847fa5ae73dc863ea by rnk
[gn build] Update build for new OpenMP tablegen logic

Ports 1a70077b5a64189d9c04d1a2d7ea6ff0e49744d6 to gn from cmake.
The file was modifiedllvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenMP/BUILD.gn
Commit 8b6f675f448e8e340b5610a637d0fa7211cc0549 by aeubanks
Fix wrong title underline length
The file was modifiedllvm/docs/AliasAnalysis.rst
Commit b6c490349d1524aefeb1c4a686411f860e6a3555 by richard
A constexpr virtual function is implicitly inline so should never be a
key function.
The file was addedclang/test/CodeGenCXX/vtable-constexpr.cpp
The file was modifiedclang/lib/AST/RecordLayoutBuilder.cpp
Commit 291ece0efa038000a31c93f132f6732ee8d30e89 by Matthew.Arsenault
AMDGPU/GlobalISel: Remove some selection tests which should be invalid

These use undef generic virtual register operands, which should be
rejected by the verifier.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
Commit e9eab30339a70596386b175b415167cc97e062d5 by Matthew.Arsenault
GlobalISel: Disallow undef generic virtual register uses

With an undef operand, it's possible for getVRegDef to fail and return
null. This is an edge case very little code bothered to
consider. Proper gMIR should use G_IMPLICIT_DEF instead.

I initially tried to apply this restriction to all SSA MIR, so then
getVRegDef would never fail anywhere. However, ProcessImplicitDefs
does technically run while the function is in SSA. ProcessImplicitDefs
and DetectDeadLanes would need to either move, or a new pseudo-SSA
type of function property would need to be introduced.
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was addedllvm/test/MachineVerifier/generic-vreg-undef-use.mir
Commit 679d101e7cbf26f82ed6bf3c9a73ab14a4897916 by thakis
[gn build] (semi-manually) port ce6153a5282
The file was modifiedllvm/utils/gn/secondary/libcxx/src/BUILD.gn
Commit 144e57fc9535eb30e7a9a2b691bc15bd38b68a04 by guiand
[Sanitizers] Implement interceptors for msgsnd, msgrcv

Differential Revision: https://reviews.llvm.org/D82897
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
The file was addedcompiler-rt/test/sanitizer_common/TestCases/Linux/sysmsg.c
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
Commit f9348f70c2330f3565ee01134bcba1dd38628c79 by aeubanks
[Docs][BasicAA] Rename some more basicaa -> basic-aa

Follow up to https://reviews.llvm.org/D82607.
The file was modifiedllvm/docs/WritingAnLLVMPass.rst