Changes from Git (git http://labmaster3.local/git/llvm-project.git)


  1. [Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align (details)
  2. Correctly track GCOVProfiling IR update (details)
  3. [ARM][LowOverheadLoops] Handle reductions (details)
  4. [AMDGPU] Spill more than wavesize CSR SGPRs (details)
  5. [ThinLTO] Always parse module level inline asm with At&t dialect (PR46503) (details)
  6. [clangd] Config: compile Fragment -> CompiledFragment -> Config (details)
  7. [analyzer][CrossTU] Lower CTUImportThreshold default value (details)
  8. [gn build] Port f12cd99c440 (details)
  9. [SVE] Relax merge requirement for IR based divides. (details)
  10. [AMDGPU] Correct AMDGPUUsage.rst DW_AT_LLVM_lane_pc example (details)
  11. [NFC][ARM] Add test. (details)
  12. [lldb] Scalar re-fix UB in float->int conversions (details)
Commit 28de229bc63489b9346558f4f3a57b024b53962a by gchatelet
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align

This patch is part of a series to introduce an Alignment type.
See this thread for context:
See this patch for the introduction of the type:

Differential Revision:
The file was modifiedllvm/lib/Target/Mips/MipsSEFrameLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCFastISel.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineFrameInfo.h
The file was modifiedllvm/lib/Target/ARC/ARCFrameLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/Mips/MipsMachineFunction.cpp
The file was modifiedllvm/lib/Target/X86/X86FastISel.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit ffee8040534495fa739808e6c66a7fc73eca27bb by sguelton
Correctly track GCOVProfiling IR update

Differential Revision:
The file was modifiedllvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
Commit 3ee580d0176f69a9f724469660f1d1805e0b6a06 by sam.parker
[ARM][LowOverheadLoops] Handle reductions

While validating live-out values, record instructions that look like
a reduction. This will comprise of a vector op (for now only vadd),
a vorr (vmov) which store the previous value of vadd and then a vpsel
in the exit block which is predicated upon a vctp. This vctp will
combine the last two iterations using the vmov and vadd into a vector
which can then be consumed by a vaddv.

Once we have determined that it's safe to perform tail-predication,
we need to change this sequence of instructions so that the
predication doesn't produce incorrect code. This involves changing
the register allocation of the vadd so it updates itself and the
predication on the final iteration will not update the falsely
predicated lanes. This mimics what the vmov, vctp and vpsel do and
so we then don't need any of those instructions.

Differential Revision:
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
The file was modifiedllvm/include/llvm/CodeGen/ReachingDefAnalysis.h
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
Commit 91823163955859abbdcad5901d765aeae860939e by Saiyedul.Islam
[AMDGPU] Spill more than wavesize CSR SGPRs

In case of more than wavesize CSR SGPR spills, lanes of reserved VGPR were getting
overwritten due to wrap around.

Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and when one
of the two conditions is true:
1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet reserved.
2. All spill lanes of reserved VGPR(s) are full and another spill lane is required.

Reviewed By: arsenm, kerbowa

Differential Revision:
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
Commit a8e582c8307ba1d33c05d272b5c1b755fa809b51 by hans
[ThinLTO] Always parse module level inline asm with At&t dialect (PR46503)

clang-cl passes -x86-asm-syntax=intel to the cc1 invocation so that
assembly listings produced by the /FA flag are printed in Intel dialect.
That flag however should not affect the *parsing* of inline assembly in
the program. (See r322652)

When compiling normally, AsmPrinter::emitInlineAsm is used for
assembling and defaults to At&t dialect. However, when compiling for
ThinLTO, the code which parses module level inline asm to find symbols
for the symbol table was failing to set the dialect. This patch fixes
that. (See the bug for more details.)

Differential revision:
The file was addedclang/test/CodeGen/thinlto-inline-asm.c
The file was modifiedllvm/lib/Object/ModuleSymbolTable.cpp
Commit f12cd99c440a83d53a8717a9c8cdc4df41f39f3d by sam.mccall
[clangd] Config: compile Fragment -> CompiledFragment -> Config

Subscribers: mgorny, ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision:
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/unittests/ConfigYAMLTests.cpp
The file was addedclang-tools-extra/clangd/ConfigProvider.h
The file was addedclang-tools-extra/clangd/unittests/ConfigCompileTests.cpp
The file was addedclang-tools-extra/clangd/ConfigCompile.cpp
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was addedclang-tools-extra/clangd/unittests/ConfigTesting.h
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
Commit 52f65323660051a5d039d475edfd4a3018682dcb by endre.fulop
[analyzer][CrossTU] Lower CTUImportThreshold default value

The default value of 100 makes the analysis slow. Projects of considerable
size can take more time to finish than it is practical. The new default
setting of 8 is based on the analysis of LLVM itself. With the old default
value of 100 the analysis time was over a magnitude slower. Thresholding the
load of ASTUnits is to be extended in the future with a more fine-tuneable
solution that accomodates to the specifics of the project analyzed.

Reviewers: martong, balazske, Szelethus

Subscribers: whisperity, xazax.hun, baloghadamsoftware, szepet, rnkovacs, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, Charusso, steakhal, ASDenysPetrov, cfe-commits

Tags: #clang

Differential Revision:
The file was modifiedclang/test/Analysis/analyzer-config.c
The file was modifiedclang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
Commit 9d347f6efa3018faf2fa159e25830817f4d2f41d by llvmgnsyncbot
[gn build] Port f12cd99c440
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/
Commit a1aed80a35f3f775cdb1d68c4388723691abc0dd by paul.walker
[SVE] Relax merge requirement for IR based divides.

We currently lower SDIV to SDIV_MERGE_OP1. This forces the value
for inactive lanes in a way that can hamper register allocation,
however, the lowering has no requirement for inactive lanes.

Instead this patch replaces SDIV_MERGE_OP1 with SDIV_PRED thus
freeing the register allocator. Once done the only user of
SDIV_MERGE_OP1 is intrinsic lowering so I've removed the node
and perform ISel on the intrinsic directly. This also allows
us to implement MOVPRFX based zeroing in the same manner as SUB.

This patch also renames UDIV_MERGE_OP1 and [F]ADD_MERGE_OP1 for
the same reason but in the ADD cases the ISel code is already
as required.

Differential Revision:
The file was modifiedllvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/
Commit 76b2d9cbebd227d42e2099a0eb89c800b945997a by Tony.Tye
[AMDGPU] Correct AMDGPUUsage.rst DW_AT_LLVM_lane_pc example

- Correct typo of DW_OP_xaddr to DW_OP_addrx in AMDGPUUsage.rst for
  DW_AT_LLVM_lane_pc example.

Change-Id: I1b0ee2b24362a0240388e4c2f044c1d4883509b9
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit f0ecfb789bb2d3de57876927e03a5c26da8419c8 by sam.parker
[NFC][ARM] Add test.
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
Commit 8270a903baf55122289499ba00a979e9c04dcd44 by pavel
[lldb] Scalar re-fix UB in float->int conversions

The refactor in 48ca15592f1 reintroduced UB when converting out-of-bounds
floating point numbers to integers -- the behavior for ULongLong() was
originally fixed in r341685, but did not survive my refactor because I
based my template code on one of the methods which did not have this

This time, I apply the fix to all float->int conversions, instead of
just the "double->unsigned long long" case. I also use a slightly
simpler version of the code, with fewer round-trips
(APFloat->APSInt->native_int vs

I also add some unit tests for the conversions.
The file was modifiedlldb/source/Utility/Scalar.cpp
The file was modifiedlldb/unittests/Utility/ScalarTest.cpp