Started 24 days ago
Took 3 hr 18 min on green-dragon-05

Success Build #17732 (Sep 30, 2020 8:21:16 AM)

Changes

Git (git http://labmaster3.local/git/llvm-project.git)

  1. [clangd] Fix fuzzer build after 7ba0779fbb41b6fa8 (detail)
  2. [clangd][remote] Make sure relative paths are absolute with respect to posix style (detail)
  3. [AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer (detail)
  4. [SplitKit] Cope with no live subranges in defFromParent (detail)
  5. [SystemZ]  Support bare nop instructions (detail)
  6. [MLIR][SPIRV] Support different function control in (de)serialization (detail)
  7. [X86] Support Intel Key Locker (detail)
  8. [gn build] Port 413577a8790 (detail)
  9. [InstCombine] recognizeBSwapOrBitReverseIdiom - assert for correct bit providence indices. NFCI. (detail)
  10. [InstCombine] recognizeBSwapOrBitReverseIdiom - recognise zext(bswap(trunc(x))) patterns (PR39793) (detail)
  11. [mlir] Added support for rank reducing subviews (detail)
  12. [NFC][ARM] Add more LowOverheadLoop tests. (detail)
  13. [mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments (detail)
  14. [SCEV] Verify that all mapped SCEV AddRecs refer to valid loops. (detail)
  15. InstCombine] collectBitParts - cleanup variable names. NFCI. (detail)
  16. [InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI. (detail)
  17. [RDA] isSafeToDefRegAt: Look at global uses (detail)
  18. [InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI. (detail)
  19. [InstCombine] Add PR47191 bswap tests (detail)
  20. [lldb] Fix FreeBSD Arm Process Plugin build (detail)
  21. [VPlan] Change recipes to inherit from VPUser instead of a member var. (detail)
  22. [lldb] [Process/NetBSD] Fix operating on ftag register (detail)
  23. [InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI. (detail)
  24. [InstCombine] Remove %tmp variable names from bswap tests (detail)
  25. [InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI. (detail)
  26. [clangd] Fix invalid UTF8 when extracting doc comments. (detail)
  27. [PowerPC] Remove support for VRSAVE save/restore/update. (detail)
  28. [GlobalISel] Fix incorrect setting of ValNo when splitting (detail)
  29. Move AffineMapAttr into BaseOps.td (detail)
  30. [sanitizers] Fix internal__exit on Solaris (detail)
  31. [NFC][FE] Replace TypeSize with StorageUnitSize (detail)
  32. Reapply "RegAllocFast: Rewrite and improve" (detail)
  33. RegAllocFast: Add extra DBG_VALUE for live out spills (detail)
  34. LiveDebugValues: Fix typos and indentation (detail)
  35. GlobalISel: Assert if MoreElements uses a non-vector type (detail)
  36. [InstCombine] Remove %tmp variable names from bswap-fold tests (detail)
  37. [FE] Use preferred alignment instead of ABI alignment for complete object when applicable (detail)
  38. [mlir][Linalg] Generalize the logic to compute reassociation maps (detail)
  39. [InstCombine] Add bswap(trunc(bswap(x))) -> trunc(lshr(x, c)) vector tests (detail)
  40. [InstCombine] Fix bswap(trunc(bswap(x))) -> trunc(lshr(x, c)) vector support (detail)
  41. [PowerPC] Avoid unused variable warning in Release builds (detail)
  42. [PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9 (detail)
  43. [InstCombine] Add tests for 'partial' bswap patterns (detail)
  44. [NFC][regalloc] Make VirtRegAuxInfo part of allocator state (detail)

Started by an SCM change

Started by timer (3 times)

This run spent:

  • 3 hr 2 min waiting;
  • 3 hr 18 min build duration;
  • 6 hr 21 min total from scheduled to completion.
Revision: d6de40f8865e2c016731f9b63d8a0a218ce1b74f
  • origin/master
Revision: 05481260c40e502d68e8d523b66eb8e23641c8b9
  • refs/remotes/origin/master
Test Result (no failures)