[Jenkins]Jenkins

SuccessChanges

Summary

  1. [AMDGPU] Remove gds operand from ds_gws_* MachineInstrs (details)
  2. [libc++] Remove additional uses of std::rand() missed by 63aeadb4849d (details)
  3. [VE] Change to use integrated assembly by defualt (details)
  4. [ARM] Add IT block generation test (details)
  5. [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz (details)
  6. [mlir][Linalg] Make Linalg fusion a test pass (details)
  7. [InstCombine] visitShl - ensure inner shifts have inrange amounts (details)
  8. [NFC] Add more tests for DISubprogram verifier (details)
  9. [sanitizer] Print errno for report file open failure (details)
  10. [AMDGPU] Use pseudo instructions for readlane/writelane (details)
  11. [MC] Error for .globl/.local which change the symbol binding and warn for .weak (details)
  12. [x86] add test for umul intrinsic costs; NFC (details)
  13. [AMDGPU] Add __builtin_amdgcn_grid_size (details)
  14. [X86] Add PR46393 test case (details)
Commit 7a79921edd74e81a05f15491e5cdb093c653e06c by jay.foad
[AMDGPU] Remove gds operand from ds_gws_* MachineInstrs

The operand value was always 1 (except in some bad MIR tests) so it was
redundant.

Differential Revision: https://reviews.llvm.org/D90378
The file was modifiedllvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-m0.mir
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/gws-hazards.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-gws.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
Commit bd8884f05e7586dd09aaab843c07361414343916 by Louis Dionne
[libc++] Remove additional uses of std::rand() missed by 63aeadb4849d
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/to_string.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/right_shift_eq.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/flip_all.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/set_one.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/op_xor_eq.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.operators/op_or.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/op_eq_eq.pass.cpp
The file was addedlibcxx/test/std/utilities/template.bitset/bitset_test_cases.h
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/left_shift.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.operators/op_not.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/op_and_eq.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/index.pass.cpp
The file was removedlibcxx/test/std/utilities/template.bitset/bitset.members/bitset_test_cases.h
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/left_shift_eq.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/op_or_eq.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/reset_one.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/flip_one.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/index_const.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/not_all.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/count.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/right_shift.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.operators/op_and.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/test.pass.cpp
Commit b5ac3721c8a497ebf33a9d0cc0d300564b0cefe1 by marukawa
[VE] Change to use integrated assembly by defualt

We've implemented integrated assembler.  Now, we change to use
integrated assembler by default.  Update a regression test also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90396
The file was modifiedclang/lib/Driver/ToolChains/VEToolchain.h
The file was modifiedclang/test/Driver/ve-toolchain.c
Commit 7b8de9fc6bce01daed49d3f6a8bd71a25e8c717f by nicholas.guy
[ARM] Add IT block generation test

D88496 introduces some new behaviour to IT block generation,
behaviour which is not covered by the current unit tests.
This adds one to cover it

Differential Revision: https://reviews.llvm.org/D90398
The file was addedllvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
Commit eb9fe24eaf2d602a5b5b59d253ad4946d850bd54 by nicholas.guy
[ARM] Fix IT block generation after Thumb2SizeReduce with -Oz

Fixes a regression caused by D82439, in which IT blocks were no longer being generated when -Oz is present.

Differential Revision: https://reviews.llvm.org/D88496
The file was modifiedllvm/test/CodeGen/Thumb2/constant-hoisting.ll
The file was modifiedllvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
Commit 9b17bf2e54c71b36bf28fbab05698fb73ea8dda9 by nicolas.vasilache
[mlir][Linalg] Make Linalg fusion a test pass

Linalg "tile-and-fuse" is currently exposed as a Linalg pass "-linalg-fusion" but only the mechanics of the transformation are currently relevant.
Instead turn it into a "-test-linalg-greedy-fusion" pass which performs canonicalizations to enable more fusions to compose.
This allows dropping the OperationFolder which is not meant to be used with the pattern rewrite infrastructure.

Differential Revision: https://reviews.llvm.org/D90394
The file was modifiedmlir/test/Dialect/Linalg/fusion-indexed-generic.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.td
The file was modifiedmlir/test/Dialect/Linalg/fusion.mlir
The file was modifiedmlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/test/lib/Transforms/TestLinalgFusionTransforms.cpp
The file was modifiedmlir/test/Dialect/Linalg/fusion-2-level.mlir
Commit dcb3dc101d80a5786f7f897f0090c081d2912443 by llvm-dev
[InstCombine] visitShl - ensure inner shifts have inrange amounts

Noticed when fixing OSS Fuzz #26716
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
The file was modifiedllvm/test/Transforms/InstCombine/shift.ll
Commit abf31f278cb629d8bc7f1683b7bfceb8d3f011c2 by scott.linder
[NFC] Add more tests for DISubprogram verifier

Minimum amount of tests to cover (most) of the DISubprogram verifier
checks.

Reviewed By: vsk

Differential Revision: https://reviews.llvm.org/D90340

Change-Id: Icd25dac64f87f6dcf67ff3443eb4f95af18d05a8
The file was addedllvm/test/DebugInfo/Generic/verifier-invalid-disubprogram.ll
Commit 81f7b96ed0a2295e0b82ca185019370ac8e1895e by tejohnson
[sanitizer] Print errno for report file open failure

To help debug failures, specifically the llvm-avr-linux bot failure from
5c20d7db9f2791367b9311130eb44afecb16829c:

http://lab.llvm.org:8011/#/builders/112/builds/407/steps/5/logs/FAIL__MemProfiler-x86_64-linux-dynamic__log_path_t

Also re-enable the failing test which I temporarily disabled, to
see if this change will help identify why that particular log file can't
be opened for write on that bot (when another log file in the same
directory could earlier in the test).

Differential Revision: https://reviews.llvm.org/D90120
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_file.cpp
The file was modifiedcompiler-rt/test/memprof/TestCases/log_path_test.cpp
Commit 58de4b205310d18614eabdcbaa1772e9fc090df3 by jay.foad
[AMDGPU] Use pseudo instructions for readlane/writelane

This reverts r227987 "R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2".

All the codegen changes are caused by the post-RA scheduler no longer
treating readlane/writelane as scheduling barriers due to having
unmodelled side effects. (The pseudos are hasSideEffects = 0, but the
real instructions are hasSideEffects = ? which TableGen conservatively
treats as 1.)

Differential Revision: https://reviews.llvm.org/D90401
The file was modifiedllvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-realign.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill192.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/csr-gfx10.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sibling-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
Commit 8f8b5e5587c3e204f21db975a0a76d4462ce3c57 by i
[MC] Error for .globl/.local which change the symbol binding and warn for .weak

GNU as let .weak override .globl since binutils-gdb
5ca547dc2399a0a5d9f20626d4bf5547c3ccfddd (1996) while MC lets the last
directive win (PR38921).

This caused an issue to Linux's powerpc port which has been fixed by
http://git.kernel.org/linus/968339fad422a58312f67718691b717dac45c399

Binding overriding is error-prone. This patch disallows a changed binding.
(https://sourceware.org/pipermail/binutils/2020-March/000299.html )

Our behavior regarding `.globl x; .weak x` matches GNU as. Such usage is
still suspicious but we issue a warning for now. We may upgrade it to an
error in the future.

Reviewed By: jhenderson, nickdesaulniers

Differential Revision: https://reviews.llvm.org/D90108
The file was modifiedllvm/lib/MC/MCELFStreamer.cpp
The file was addedllvm/test/MC/ELF/symbol-binding-changed.s
Commit d5a75e7738d0ca2955b3b10a7d4631110f930b67 by spatel
[x86] add test for umul intrinsic costs; NFC
The file was modifiedllvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll
Commit dee7704829bd421ad3cce4b2132d28f4459b7319 by jonathanchesterfield
[AMDGPU] Add __builtin_amdgcn_grid_size

[AMDGPU] Add __builtin_amdgcn_grid_size

Similar to D76772, loads the data from the dispatch pointer. Marked invariant.

Patch also updates the openmp devicertl to use this builtin.

Reviewed By: yaxunl

Differential Revision: https://reviews.llvm.org/D90251
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/src/target_impl.hip
The file was modifiedclang/include/clang/Basic/BuiltinsAMDGPU.def
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn.cl
Commit 93ebefb9ee75143625d701250e69e701df4a7702 by llvm-dev
[X86] Add PR46393 test case
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll