Started 26 days ago
Took 56 min

Success Build #19963 (Oct 30, 2020 2:33:04 PM)

Changes
  1. [mlir] Move some linalg patterns around. (details)
  2. [MLIR][SPIRV] Start module combiner. (details)
  3. [Legalize] Add legalizations for VECREDUCE_SEQ_FADD (details)
  4. [mlir] Add BufferResultsToOutParams pass. (details)
  5. [FileCheck] Address unused prefixes in tests (details)
  6. hwasan: Support for outlined checks in the Linux kernel. (details)
  7. Revert "[TTI] Add VecPred argument to getCmpSelInstrCost." (details)
  8. Revert "[SLP] Consider alternatives for cost of select instructions." (details)

Started by an SCM change (43 times)

This run spent:

  • 42 min waiting;
  • 56 min build duration;
  • 1 hr 38 min total from scheduled to completion.
Revision: a1b53db32418cb6ed6f5b2054d15a22b5aa3aeb9
  • refs/remotes/origin/master
Revision: 09f45064d988db56acc81166eec1ad8a97d3f16d
  • refs/remotes/origin/master
Test Result (no failures)