SuccessChanges

Summary

  1. Implement DW_OP_convert (details)
  2. AMDGPU/GlobalISel: First pass at attempting to legalize load/stores (details)
  3. [RISCV] Support llvm-objdump -M no-aliases and -M numeric (details)
  4. AMDGPU/GlobalISel: Legalize constant 32-bit loads (details)
  5. AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD (details)
Commit 9b23df63ecd9f23bb8877783d30d1a49e895cf7c by Adrian Prantl
Implement DW_OP_convert
This patch adds basic support for DW_OP_convert[1] for integer types.
Recent versions of LLVM's optimizer may insert this opcode into DWARF
expressions. DW_OP_convert is effectively a type cast operation that
takes a reference to a base type DIE (or zero) and then casts the value
at the top of the DWARF stack to that type. Internally this works by
changing the bit size of the APInt that is used as backing storage for
LLDB's DWARF stack.
I managed to write a unit test for this by implementing a mock YAML
object file / module that takes debug info sections in yaml2obj format.
[1] Typed DWARF stack.
http://www.dwarfstd.org/ShowIssue.php?issue=140425.1
<rdar://problem/48167864>
Differential Revision: https://reviews.llvm.org/D67369
llvm-svn: 371532
The file was modifiedlldb/source/Core/Section.cpp
The file was modifiedlldb/source/Utility/Scalar.cpp
The file was modifiedlldb/include/lldb/Utility/Scalar.h
The file was modifiedlldb/source/Expression/DWARFExpression.cpp
The file was modifiedlldb/unittests/Expression/DWARFExpressionTest.cpp
The file was modifiedlldb/unittests/Utility/ScalarTest.cpp
The file was modifiedlldb/include/lldb/Core/Section.h
Commit c0ceca5883060bfaf501007d76640821d825828b by Matthew.Arsenault
AMDGPU/GlobalISel: First pass at attempting to legalize load/stores
There's still a lot more to do, but this handles decomposing due to
alignment. I've gotten it to the point where nothing crashes or infinite
loops the legalizer.
llvm-svn: 371533
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load.mir
Commit d57de491be0ba4fea88566bc0803773c53dc8414 by selliott
[RISCV] Support llvm-objdump -M no-aliases and -M numeric
Summary: Now that llvm-objdump allows target-specific options, we match
the
`no-aliases` and `numeric` options for RISC-V, as supported by GNU
objdump.
This is done by overriding the variables used for the command-line
options, so that the command-line options are still supported.
This patch updates all tests using `llvm-objdump -riscv-no-aliases` to
use
`llvm-objdump -M no-aliases`.
Reviewers: luismarques, asb
Reviewed By: luismarques, asb
Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos,
sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng,
edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX,
jocewei, psnobl, benna, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66139
llvm-svn: 371534
The file was modifiedllvm/test/MC/RISCV/rv64c-hints-valid.s
The file was modifiedllvm/test/MC/RISCV/rvd-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32f-valid.s
The file was modifiedllvm/test/MC/RISCV/compress-rv32f.s
The file was modifiedllvm/test/MC/RISCV/align.s
The file was modifiedllvm/test/MC/RISCV/rv32c-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64dc-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64f-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64f-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/csr-aliases.s
The file was modifiedllvm/test/MC/RISCV/numeric-reg-names-f.s
The file was modifiedllvm/test/MC/RISCV/rv64i-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rvi-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/compress-cjal.s
The file was modifiedllvm/test/MC/RISCV/rv32fc-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rvc-hints-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/compress.ll
The file was modifiedllvm/test/MC/RISCV/rv64a-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64d-valid.s
The file was modifiedllvm/test/MC/RISCV/rva-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64a-aliases-valid.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
The file was modifiedllvm/test/MC/RISCV/rv32d-valid.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was modifiedllvm/test/MC/RISCV/rv64c-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/option-rvc.s
The file was modifiedllvm/test/MC/RISCV/rv32e-invalid.s
The file was modifiedllvm/test/MC/RISCV/rv64i-valid.s
The file was modifiedllvm/test/MC/RISCV/priv-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64d-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/numeric-reg-names.s
The file was modifiedllvm/test/MC/RISCV/rv32fc-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32i-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64c-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32-relaxation.s
The file was modifiedllvm/test/MC/RISCV/rv32m-valid.s
The file was modifiedllvm/test/MC/RISCV/option-mix.s
The file was modifiedllvm/test/MC/RISCV/rv32e-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32a-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32dc-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32i-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/compress-rv32d.s
The file was modifiedllvm/test/MC/RISCV/rv64m-valid.s
The file was modifiedllvm/test/MC/RISCV/numeric-reg-names-d.s
The file was modifiedllvm/test/MC/RISCV/rvf-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/fixups.s
The file was modifiedllvm/test/MC/RISCV/compress-rv32i.s
The file was modifiedllvm/test/MC/RISCV/rvc-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32c-only-valid.s
The file was modifiedllvm/test/MC/RISCV/fixups-compressed.s
The file was modifiedllvm/test/CodeGen/RISCV/compress-inline-asm.ll
The file was modifiedllvm/test/MC/RISCV/rvdc-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/option-norvc.ll
The file was modifiedllvm/test/CodeGen/RISCV/option-rvc.ll
The file was modifiedllvm/test/MC/RISCV/cnop.s
The file was modifiedllvm/test/MC/RISCV/rv32c-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64-relaxation.s
The file was modifiedllvm/test/MC/RISCV/compress-rv64i.s
Commit ad6a8b83cdc35019cc0431286f3fbacf7d184781 by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize constant 32-bit loads
Legalize by casting to a 64-bit constant address. This isn't how the DAG
implements it, but it should.
llvm-svn: 371535
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
Commit da027275c666183efb9434ece31ef0d92fcf9f2b by Matthew.Arsenault
AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD
llvm-svn: 371536
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp