Started 7 days 6 hr ago
Took 34 min on green-dragon-22

Success Build rL:362914 - C:362887 - #62205 (Jun 9, 2019 5:40:50 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 362914
  • http://llvm.org/svn/llvm-project/cfe/trunk : 362887
Changes
  1. [X86] Convert f32/f64 FANDN/FAND/FOR/FXOR to vector logic ops and scalar_to_vector/extract_vector_elts to reduce isel patterns.

    Previously we did the equivalent operation in isel patterns with
    COPY_TO_REGCLASS operations to transition. By inserting
    scalar_to_vetors and extract_vector_elts before isel we can
    allow each piece to be selected individually and accomplish the
    same final result.

    I ideally we'd use vector operations earlier in lowering/combine,
    but that looks to be more difficult.

    The scalar-fp-to-i64.ll changes are because we have a pattern for
    using movlpd for store+extract_vector_elt. While an f64 store
    uses movsd. The encoding sizes are the same. (detail/ViewSVN)
    by ctopper

Started by an SCM change

This run spent:

  • 6.2 sec waiting;
  • 34 min build duration;
  • 34 min total from scheduled to completion.
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 62,159.
  • Still 20 days before reaching the previous zero warnings highscore.
Test Result (no failures)