Started 8 days 12 hr ago
Took 37 min on green-dragon-03

Success Build rL:362964 - C:362959 - #62237 (Jun 10, 2019 9:55:51 AM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 362964
  • http://llvm.org/svn/llvm-project/cfe/trunk : 362959
Changes
  1. [llvm-mca] Enable bottleneck analysis when flag -all-views is specified.

    Bottleneck Analysis is one of the many views available in llvm-mca. Therefore,
    it should be enabled when flag -all-views is passed in input to the tool. (detail/ViewSVN)
    by adibiagio
  2. [FastISel] Skip creating unnecessary vregs for arguments

    This behavior was added in r130928 for both FastISel and SD, and then
    disabled in r131156 for FastISel.

    This re-enables it for FastISel with the corresponding fix.

    This is triggered only when FastISel can't lower the arguments and falls
    back to SelectionDAG for it.

    FastISel contains a map of "register fixups" where at the end of the
    selection phase it replaces all uses of a register with another
    register that FastISel sometimes pre-assigned. Code at the end of
    SelectionDAGISel::runOnMachineFunction is doing the replacement at the
    very end of the function, while other pieces that come in before that
    look through the MachineFunction and assume everything is done. In this
    case, the real issue is that the code emitting COPY instructions for the
    liveins (physreg to vreg) (EmitLiveInCopies) is checking if the vreg
    assigned to the physreg is used, and if it's not, it will skip the COPY.
    If a register wasn't replaced with its assigned fixup yet, the copy will
    be skipped and we'll end up with uses of undefined registers.

    This fix moves the replacement of registers before the emission of
    copies for the live-ins.

    The initial motivation for this fix is to enable tail calls for
    swiftself functions, which were blocked because we couldn't prove that
    the swiftself argument (which is callee-save) comes from a function
    argument (live-in), because there was an extra copy (vreg to vreg).

    A few tests are affected by this:

    * llvm/test/CodeGen/AArch64/swifterror.ll: we used to spill x21
    (callee-save) but never reload it because it's attached to the return.
    We now don't even spill it anymore.
    * llvm/test/CodeGen/*/swiftself.ll: we tail-call now.
    * llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll: I believe this
    test was not really testing the right thing, but it worked because the
    same registers were re-used.
    * llvm/test/CodeGen/ARM/cmpxchg-O0.ll: regalloc changes
    * llvm/test/CodeGen/ARM/swifterror.ll: get rid of a copy
    * llvm/test/CodeGen/Mips/*: get rid of spills and copies
    * llvm/test/CodeGen/SystemZ/swift-return.ll: smaller stack
    * llvm/test/CodeGen/X86/atomic-unordered.ll: smaller stack
    * llvm/test/CodeGen/X86/swifterror.ll: same as AArch64
    * llvm/test/DebugInfo/X86/dbg-declare-arg.ll: stack size changed

    Differential Revision: https://reviews.llvm.org/D62361 (detail/ViewSVN)
    by thegameg

Started by an SCM change

This run spent:

  • 9.2 sec waiting;
  • 37 min build duration;
  • 37 min total from scheduled to completion.
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 62,234.
  • Still 22 days before reaching the previous zero warnings highscore.
Test Result (no failures)