Started 4 days 13 hr ago
Took 1 hr 52 min on green-dragon-19

Success Build rL:363411 - C:363390 - #62360 (Jun 14, 2019 8:24:16 AM)

  • : 363411
  • : 363390
  1. [x86] move vector shift tests for PR37428; NFC

    As suggested in the post-commit thread for rL363392 - it's
    wasteful to have so many runs for larger tests. AVX1/AVX2
    is what shows the diff and probably what matters most going
    forward. (detail/ViewSVN)
    by spatel
  2. GlobalISel: Avoid producing Illegal copies in RegBankSelect

    Avoid producing illegal register bank copies for reg_sequence and
    phi. The default implementation assumes it is possible to pick any
    operand's bank and use that for the result, introducing a copy for
    operands with a different bank. This does not check for illegal
    copies. It is not legal to introduce a VGPR->SGPR copy, so any VGPR
    operand requires the result to be a VGPR.

    The changes in getInstrMappingImpl aren't strictly necessary, since
    AMDGPU now just bypasses this for reg_sequence/phi. This could be
    replaced with an assert in case other targets run into this. It is
    currently responsible for producing the error for unsatisfiable
    copies, but this will be better served with a verifier check.

    For phis, for now assume any undetermined operands must be
    VGPRs. Eventually, this needs to be able to defer mapping these
    operations. This also does not yet have a way to check for whether the
    block is in a divergent region. (detail/ViewSVN)
    by arsenm
  3. [CodeGenPrepare] propagate debuginfo when copying a shuffle (detail/ViewSVN)
    by spatel
  4. [Attributor] Disable the Attributor by default and fix a comment (detail/ViewSVN)
    by jdoerfert
  5. [Attributor] Introduce bit-encodings for abstract states

    The IntegerState, and its sepecialization BooleanState, can be used to
    simplify the implementation of abstract attributes. The two abstract
    state implementations provide storage and helpers to deal with bit-wise
    encoded state.

    Subscribers: hiraditya, bollu, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by jdoerfert
  6. AMDGPU: Fold readlane intrinsics of constants

    I'm not 100% sure about this, since I'm worried about IR transforms
    that might end up introducing divergence downstream once replaced with
    a constant, but I haven't come up with an example yet. (detail/ViewSVN)
    by arsenm
  7. [ARM] Add MVE horizontal accumulation instructions

    This is the family of vector instructions that combine all the lanes
    in their input vector(s), and output a value in one or two GPRs.

    Differential Revision: (detail/ViewSVN)
    by miyuki
  8. Revert "Revert r363377: [yaml2obj] - Allow setting custom section types for implicit sections."

    LLD test case will be fixed in a following commit.

    Original commit message:

    [yaml2obj] - Allow setting custom section types for implicit sections.

    We were hardcoding the final section type for sections that
    are usually implicit. The patch fixes that.

    This also fixes a few issues in existent test cases and removes
    one precompiled object.

    Differential revision: (detail/ViewSVN)
    by grimar
  9. Revert r363377: [yaml2obj] - Allow setting custom section types for implicit sections.

    This reverts commit r363377 because lld's ELF/invalid/undefined-local-symbol-in-dso.test
    test started failing after this commit. (detail/ViewSVN)
    by ruiu
  10. Fix failing test on ARM buildbot

    r363261 caused test failure on 32-bit ARM buildbot,
    because of unsigned integer overflow. This patch
    fixes it changing offset type from size_t to uint64_t. (detail/ViewSVN)
    by evgeny777
  11. [x86] add test for original example in PR37428; NFC

    The reduced case may avoid complications seen in this larger function. (detail/ViewSVN)
    by spatel
  12. RegBankSelect: Remove checks for invalid mappings

    Avoid a check for valid and a set of redundant asserts. The place
    InstructionMapping is constructed asserts all of the default fields
    are passed anyway for an invalid mapping, so don't overcomplicate
    this. (detail/ViewSVN)
    by arsenm

Started by an SCM change (10 times)

This run spent:

  • 1 hr 43 min waiting;
  • 1 hr 52 min build duration;
  • 3 hr 36 min total from scheduled to completion.
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 62,284.
  • Still 20 days before reaching the previous zero warnings highscore.
Test Result (no failures)