Started 6 days 13 hr ago
Took 11 min on green-dragon-19

Success Build rL:366008 - C:366007 - #63142 (Jul 13, 2019 8:48:59 AM)

  • : 366008
  • : 366007
  1. [ARM] Add sign and zero extend patterns for MVE

    The vmovlb instructions can be uses to sign or zero extend vector registers
    between types. This adds some patterns for them and relevant testing. The
    VBICIMM generation is also put behind a hasNEON check (as is already done for

    Code originally by David Sherwood.

    Differential Revision: (detail/ViewSVN)
    by dmgreen

Started by an SCM change

This run spent:

  • 3 min 19 sec waiting;
  • 11 min build duration;
  • 14 min total from scheduled to completion.
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 63,111.
  • Still 21 days before reaching the previous zero warnings highscore.
Test Result (no failures)