SuccessChanges

Summary

  1. [clang-tools-extra] fix the check for if '-latomic' is necessary (details)
  2. [AArch64] Add BIT/BIF support. (details)
Commit 1d40c4150630729a9c1ce5119a8027dac93a5b2d by luismarques
[clang-tools-extra] fix the check for if '-latomic' is necessary

Summary:
The CheckAtomic module performs two tests to determine if passing
'-latomic' to the linker is required: one for 64-bit atomics, and
another for non-64-bit atomics. clangd only uses the result from
HAVE_CXX_ATOMICS64_WITHOUT_LIB. This is incomplete because there are
uses of non-64-bit atomics in the code, such as the ReplyOnce::Replied
of type std::atomic<bool> defined in clangd/ClangdLSPServer.cpp.

Fix by also checking for the result of HAVE_CXX_ATOMICS_WITHOUT_LIB.

See also: https://reviews.llvm.org/D68964

Reviewers: ilya-biryukov, nridge, kadircet, beanz, compnerd, luismarques
Reviewed By: luismarques
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69869
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
Commit b6a9fe209992789be3ed95664d25196361cfad34 by Pavel.Iliin
[AArch64] Add BIT/BIF support.

This patch added generation of SIMD bitwise insert BIT/BIF instructions.
In the absence of GCC-like functionality for optimal constraints satisfaction
during register allocation the bitwise insert and select patterns are matched
by pseudo bitwise select BSP instruction with not tied def.
It is expanded later after register allocation with def tied
to BSL/BIT/BIF depending on operands registers.
This allows to get rid of redundant moves.

Reviewers: t.p.northover, samparker, dmgreen

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D74147
The file was modifiedllvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
The file was modifiedllvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
The file was modifiedllvm/test/CodeGen/AArch64/sat-add.ll
The file was modifiedllvm/test/CodeGen/AArch64/sqrt-fastmath.ll
The file was modifiedllvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask-const.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SchedExynosM3.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SchedExynosM4.td
The file was addedllvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SchedA57.td
The file was modifiedllvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
The file was modifiedllvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SchedKryoDetails.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SchedExynosM5.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SchedCyclone.td
The file was modifiedllvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td