Started 10 days ago
Took 31 min on green-dragon-16

Failed Build rL:363343 - C:363343 - #57490 (Jun 13, 2019 5:12:15 PM)

  • : 363343
  • : 363343
  • : 363327
  • : 362745
  • : 363283
  • : 363333
  • : 363296
  1. Revert "[Remarks] Refactor optimization remarks setup"

    This reverts commit 6e6e3af55bb97e1a4c97375c15a2b0099120c5a7.

    This breaks greendragon. (detail/ViewSVN)
    by thegameg
  2. [Coverage] Speculative fix for r363325 for an older compiler

    It looks like an older version of gcc can't figure out that it needs to
    move a unique_ptr while implicitly constructing an Expected object. (detail/ViewSVN)
    by Vedant Kumar
  3. [AMDGPU] gfx1010 wave32 clang support

    Differential Revision: (detail/ViewSVN)
    by rampitec
  4. Remove unused SK_LValueToRValue initialization step.

    In addition to being unused and duplicating code, this was also wrong
    (it didn't properly mark the operand as being potentially not odr-used). (detail/ViewSVN)
    by rsmith
  5. [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32

    Differential Revision: (detail/ViewSVN)
    by rampitec
  6. PR23833, DR2140: an lvalue-to-rvalue conversion on a glvalue of type
    nullptr_t does not access memory.

    We now reuse CK_NullToPointer to represent a conversion from a glvalue
    of type nullptr_t to a prvalue of nullptr_t where necessary.

    This reinstates r345562, reverted in r346065, now that CodeGen's
    handling of non-odr-used variables has been fixed. (detail/ViewSVN)
    by rsmith
  7. [llvm-objcopy] Fix sparc target endianness

    Summary: AFAIK, the "sparc" target is big endian and the target for 32-bit little-endian SPARC is denoted as "sparcel". This patch fixes the endianness of "sparc" target and adds "sparcel" target for 32-bit little-endian SPARC.

    Reviewers: espindola, alexshap, rupprecht, jhenderson

    Reviewed By: jhenderson

    Subscribers: jyknight, emaste, arichardson, fedor.sergeev, jakehehrlich, MaskRay, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by seiya
  8. Use fully qualified name when printing S_CONSTANT records

    Before it was using the fully qualified name only for static data members.
    Now it does for all variable names to match MSVC.

    Reviewers: rnk

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by akhuang
  9. Symbolize: Remove dead code. NFCI.

    The only caller of SymbolizableObjectFile::create passes a non-null
    DebugInfoContext and asserts that they do so. Move the assert into
    SymbolizableObjectFile::create and remove null checks.

    Differential Revision: (detail/ViewSVN)
    by pcc
  10. [libc++] Fix build with gcc 4.8

    gcc 4.8.4 (but not 5.4.0 or 7.3.0) has trouble initializing errc with {}, giving
    the error in [1]. This CL switches to explicitly using errc(0), which gcc 4.8


    Differential Revision: (detail/ViewSVN)
    by thomasanderson
  11. [AMDGPU] gfx10 documentation update. NFC. (detail/ViewSVN)
    by rampitec
  12. [GlobalISel][IRTranslator] Add debug loc with line 0 to constants emitted into the entry block.

    Constants, including G_GLOBAL_VALUE, are all emitted into the entry block which
    lets us use the vreg def assuming it dominates all other users. However, it can
    cause jumpy debug behaviour since the DebugLoc attached to these MIs are from
    a user instruction that could be in a different block.

    Fixes PR40887.

    Differential Revision: (detail/ViewSVN)
    by aemerson
  13. [X86Disassembler] Unify the EVEX and VEX code in emitContextTable. Merge the ATTR_VEXL/ATTR_EVEXL bits. NFCI

    Merging the two bits shrinks the context table from 16384 bytes to 8192 bytes.

    Remove the ATTRIBUTE_BITS macro and just create an enum directly. Then fix the ATTR_max define to be 8192 to reflect the table size so we stop hardcoding it separately. (detail/ViewSVN)
    by ctopper
  14. [MachinePiepliner] Don't check boundary node in checkValidNodeOrder

    This was exposed by PowerPC target enablement.

    In ScheduleDAG, if we haven't seen any uses in this scheduling region,
    we will create a dependence edge to ExitSU to model the live-out latency.
    This is required for vreg defs with no in-region use, and prefetches with
    no vreg def.

    When we build NodeOrder in Scheduler, we ignore these boundary nodes.
    However, when we check Succs in checkValidNodeOrder, we did not skip
    them, so we still assume all the nodes have been sorted and in order in
    Indices array. So when we call lower_bound() for ExitSU, it will return
    Indices.end(), causing memory issues in following Node access.

    Differential Revision: (detail/ViewSVN)
    by jsji
  15. [Remarks] Refactor optimization remarks setup

    * Add a common function to setup opt-remarks
    * Rename common options to the same names
    * Add error types to distinguish between file errors and regex errors (detail/ViewSVN)
    by thegameg

Started by an SCM change (12 times)

This run spent:

  • 2 hr 25 min waiting;
  • 31 min build duration;
  • 2 hr 56 min total from scheduled to completion.

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