Started 17 hr ago
Took 2 hr 35 min on green-dragon-19

Success Build rL:364215 - C:364202 - #57584 (Jun 24, 2019 11:29:51 AM)

  • : 364215
  • : 364202
  • : 364105
  • : 363952
  • : 364192
  • : 364170
  • : 364180
  1. AMDGPU/GlobalISel: Select G_TRUNC (detail/ViewSVN)
    by arsenm
  2. AMDGPU/GlobalISel: RegBankSelect for amdgcn.class (detail/ViewSVN)
    by arsenm
  3. [PowerPC][UpdateTestChecks] powerpc- triple support

    There are quite some old testcases with powerpc- triple,
    we should add this triple support so that we can update them with script.

    Differential Revision: (detail/ViewSVN)
    by jsji
  4. AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect

    Scalar extends to s64 can use S_BFE_{I64|U64}, but vector extends need
    to extend to the 32-bit half, and then to 64.

    I'm not sure what the line should be between what RegBankSelect
    handles, and what instruction select does, but for now I'm erring on
    the side of RegBankSelect for future post-RBS combines. (detail/ViewSVN)
    by arsenm
  5. [llvm-objdump] Match GNU objdump on symbol types shown in disassembly

    STT_OBJECT and STT_COMMON are dumped as data, not disassembled.

    Differential Revision: (detail/ViewSVN)
    by yuanfang
  6. [AMDGPU] Allow any value in unused src0 field in v_nop

    The LLVM disassembler assumes that the unused src0 operand of v_nop is
    zero. Other tools can put another value in that field, which is still
    valid. This commit fixes the LLVM disassembler to recognize such an
    encoding as v_nop, in the same way as we already do for s_getpc.

    Differential Revision:

    Change-Id: Iaf0363eae26ff92fc4ebc716216476adbff37a6f (detail/ViewSVN)
    by tpr
  7. [X86] Don't a vzext_movl in LowerBuildVectorv16i8/LowerBuildVectorv8i16 if there are no zeroes in the vector we're building.

    In LowerBuildVectorv16i8 we took care to use an any_extend if the first pair is in the lower 16-bits of the vector and no elements are 0. So bits [31:16] will be undefined. But we still emitted a vzext_movl to ensure that bits [127:32] are 0. If we don't need any zeroes we should be consistent and make all of 127:16 undefined.

    In LowerBuildVectorv8i16 we can just delete the vzext_movl code because we only use the scalar_to_vector when there are no zeroes. So the vzext_movl is always unnecessary.

    Found while investigating whether (vzext_movl (scalar_to_vector (loadi32)) patterns are necessary. At least one of the cases where they were necessary was where the loadi32 matched 32-bit aligned 16-bit extload. Seemed weird that we required vzext_movl for that case.

    Differential Revision: (detail/ViewSVN)
    by ctopper
  8. [X86] Cleanups and safety checks around the isFNEG

    This patch does a few things to start cleaning up the isFNEG function.

    -Remove the Op0/Op1 peekThroughBitcast calls that seem unnecessary. getTargetConstantBitsFromNode has its own peekThroughBitcast inside. And we have a separate peekThroughBitcast on the return value.
    -Add a check of the scalar size after the first peekThroughBitcast to ensure we haven't changed the element size and just did something like f32->i32 or f64->i64.
    -Remove an unnecessary check that Op1's type is floating point after the peekThroughBitcast. We're just going to look for a bit pattern from a constant. We don't care about its type.
    -Add VT checks on several places that consume the return value of isFNEG. Due to the peekThroughBitcasts inside, the type of the return value isn't guaranteed. So its not safe to use it to build other nodes without ensuring the type matches the type being used to build the node. We might be able to replace these checks with bitcasts instead, but I don't have a test case so a bail out check seemed better for now.

    Differential Revision: (detail/ViewSVN)
    by ctopper
  9. [AArch64] Regenerate vcvt tests. NFCI.

    Prep work for an upcoming patch (detail/ViewSVN)
    by rksimon
  10. [AArch64] Regenerate 2velem tests. NFCI.

    Prep work for an upcoming patch (detail/ViewSVN)
    by rksimon
  11. [AArch64] Regenerate merge-store tests. NFCI.

    Prep work for an upcoming patch (detail/ViewSVN)
    by rksimon
  12. [clang][NewPM] Add RUNS for tests that produce slightly different IR under new PM

    For CodeGenOpenCL/, the new PM produced a slightly different for
    loop, but this still checks for no loop unrolling as intended. This is
    committed separately from D63174. (detail/ViewSVN)
    by leonardchan
  13. [clang][NewPM] Remove exception handling before loading pgo sample profile data

    This patch ensures that SimplifyCFGPass comes before SampleProfileLoaderPass
    on PGO runs in the new PM and fixes clang/test/CodeGen/pgo-sample.c.

    Differential Revision: (detail/ViewSVN)
    by leonardchan
  14. [X86] Regenerate fast fadd reduction tests. NFCI

    Fix whitespace. (detail/ViewSVN)
    by rksimon
  15. AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1

    Try to fail for scc, since I don't think that should ever be produced. (detail/ViewSVN)
    by arsenm
  16. [bindings/go] Add debug information accessors

    Add debug information accessors, as provided in the following patches: (DILocation) metadata kind get/set debug location on a Value (DIScope)

    The API as proposed in this patch is similar to the current Value API,
    with a single root type and methods that are only valid for certain
    subclasses. I have considered just implementing generic Line() calls
    (that are valid on all DINodes that have a line) but the implementation
    of that got a bit awkward without support from the C API. I've also
    considered creating generic getters like a Metadata.DebugLoc() that
    returns a DebugLoc, but there is a mismatch between the Go DI nodes in
    the LLVM API and the actual DINode class hierarchy, so that's also hard
    to get right (without being confusing or breaking the API).

    Differential Revision: (detail/ViewSVN)
    by aykevl
  17. [analyzer] print() JSONify: ProgramPoint revision

    Summary: Now we also print out the filename with its path.

    Reviewers: NoQ

    Reviewed By: NoQ

    Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin,
                 mikhail.ramalho, Szelethus, donat.nagy, dkrupp, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by charusso
  18. Hexagon: Rename another copy of Register class

    For some reason clang is happy with the conflict, but MSVC is not. (detail/ViewSVN)
    by arsenm
  19. ARC: Fix -Wimplicit-fallthrough (detail/ViewSVN)
    by arsenm
  20. GlobalISel: Remove unsigned variant of SrcOp

    Force using Register.

    One downside is the generated register enums require explicit
    conversion. (detail/ViewSVN)
    by arsenm

Started by an SCM change (12 times)

This run spent:

  • 2 hr 7 min waiting;
  • 2 hr 35 min build duration;
  • 4 hr 43 min total from scheduled to completion.
LLVM/Clang Warnings: 1 warning.
    Test Result (no failures)