Started 5 days 13 hr ago
Took 6 hr 7 min on green-dragon-21

Success Build #18187 (Jun 11, 2019 10:50:36 AM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 362983
  • http://llvm.org/svn/llvm-project/cfe/trunk : 362965
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 362970
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 362745
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 362967
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 362978
Changes
  1. [demangle] Vendor extended types shouldn't be considered substitution candidates (detail/ViewSVN)
    by epilk
  2. Factor out a helper function for readability and reuse in a future patch [NFC] (detail/ViewSVN)
    by reames
  3. [Docs] [llvm-mca] Point out a caveat for using llvm-mca markers in source code.

    Summary: See: https://bugs.llvm.org/show_bug.cgi?id=42173

    Reviewers: andreadb, mattd, RKSimon, spatel

    Reviewed By: andreadb

    Subscribers: tschuett, gbedwell, llvm-commits, andreadb

    Tags: #llvm

    Patch by Max Marrone (maxpm)! Thanks!

    Differential Revision: https://reviews.llvm.org/D63040 (detail/ViewSVN)
    by mattd
  4. [clangd] Remove old hidden -use-dex-index flag (detail/ViewSVN)
    by sammccall
  5. [Tests] Add tests for D62939 (miscompiles around dead pointer IVs)

    Flesh out a collection of tests for switching to a dead IV within LFTR, both for the current miscompile, and for some cases which we should be able to handle via simple reasoning. (detail/ViewSVN)
    by reames
  6. [LFTR] Use recomputed BE count

    This was discussed as part of D62880.  The basic thought is that computing BE taken count after widening should produce (on average) an equally good backedge taken count as the one before widening.  Since there's only one test in the suite which is impacted by this change, and it's essentially equivelent codegen, that seems to be a reasonable assertion.  This change was separated from r362971 so that if this turns out to be problematic, the triggering piece is obvious and easily revertable.

    For the nestedIV example from elim-extend.ll, we end up with the following BE counts:
    BEFORE: (-2 + (-1 * %innercount) + %limit)
    AFTER: (-1 + (sext i32 (-1 + %limit) to i64) + (-1 * (sext i32 %innercount to i64))<nsw>)

    Note that before is an i32 type, and the after is an i64.  Truncating the i64 produces the i32. (detail/ViewSVN)
    by reames
  7. [PowerPC][HTM]Fix $zero is not a GPRC register for builtin_ttest

    This was found during HTM cleanup.
    Adding a test for builtin_ttest would expose following issue.

    *** Bad machine code: Illegal physical register for instruction ***
    - function:    test10
    - basic block: %bb.0 entry (0xf0e57497b58)
    - instruction: %5:crrc0 = TABORTWCI 0, $zero, 0
    - operand 2:   $zero
      $zero is not a GPRC register.
    LLVM ERROR: Found 1 machine code errors.

    Differential Revision: https://reviews.llvm.org/D63079 (detail/ViewSVN)
    by jsji
  8. [llvm-objcopy] Fix SHT_GROUP ordering.

    Summary:
    When llvm-objcopy sorts sections during finalization, it only sorts based on the offset, which can cause the group section to come after the sections it contains. This causes link failures when using gold to link objects created by llvm-objcopy.

    Fix this for now by copying GNU objcopy's behavior of placing SHT_GROUP sections first. In the future, we may want to remove this sorting entirely to more closely preserve the input file layout.

    This fixes https://bugs.llvm.org/show_bug.cgi?id=42052.

    Reviewers: jakehehrlich, jhenderson, MaskRay, espindola, alexshap

    Reviewed By: MaskRay

    Subscribers: phuongtrang148993, emaste, arichardson, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D62620 (detail/ViewSVN)
    by rupprecht
  9. [Analysis] add unit test file for VectorUtils; NFC (detail/ViewSVN)
    by spatel
  10. Prepare for multi-exit LFTR [NFC]

    This change does the plumbing to wire an ExitingBB parameter through the LFTR implementation, and reorganizes the code to work in terms of a set of individual loop exits. Most of it is fairly obvious, but there's one key complexity which makes it worthy of consideration. The actual multi-exit LFTR patch is in D62625 for context.

    Specifically, it turns out the existing code uses the backedge taken count from before a IV is widened. Oddly, we can end up with a different (more expensive, but semantically equivelent) BE count for the loop when requerying after widening.  For the nestedIV example from elim-extend, we end up with the following BE counts:
    BEFORE: (-2 + (-1 * %innercount) + %limit)
    AFTER: (-1 + (sext i32 (-1 + %limit) to i64) + (-1 * (sext i32 %innercount to i64))<nsw>)

    This is the only test in tree which seems sensitive to this difference. The actual result of using the wider BETC on this example is that we actually produce slightly better code. :)

    In review, we decided to accept that test change.  This patch is structured to preserve the old behavior, but a separate change will immediate follow with the behavior change.  (I wanted it separate for problem attribution purposes.)

    Differential Revision: https://reviews.llvm.org/D62880 (detail/ViewSVN)
    by reames
  11. Add unused symbol to thunk files to force wholearchive inclusion

    These "dynamic_runtime_thunk" object files exist to create a weak alias
    from 'foo' to 'foo_dll' for all weak sanitizer runtime symbols. The weak
    aliases are implemented as /alternatename linker options in the
    .drective section, so they are not actually in the symbol table. In
    order to force the Visual C++ linker to load the object, even with
    -wholearchive:, we have to provide at least one external symbol. Once we
    do that, it will read the .drective sections and see the weak aliases.

    Fixes PR42074 (detail/ViewSVN)
    by rnk
  12. [ELF][llvm-objdump] Treat dynamic tag values as virtual addresses instead of offsets

    The ELF gABI requires the tag values of DT_REL, DT_RELA and DT_JMPREL to be
    treated as virtual addresses. They were treated as offsets. Fixes PR41832.

    Differential Revision: https://reviews.llvm.org/D62972 (detail/ViewSVN)
    by wolfgangp
  13. [RISCV] Replace map with set in getReqFeatures

    Summary:
    Use a set in getReqFeatures() in RISCVCompressInstEmitter instead of a map
    because the index we save is not needed.

    This also fixes bug 41666.

    Reviewers: llvm-commits, apazos, asb, nickdesaulniers

    Reviewed By: asb

    Subscribers: Jim, nickdesaulniers, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D61412 (detail/ViewSVN)
    by sabuasal
  14. [libc++] Fix leading zeros in std::to_chars

    Summary:
    It is a bugfix proposal for https://bugs.llvm.org/show_bug.cgi?id=42166.

    `std::to_chars` appends leading zeros if input 64-bit value has 9, 10 or 11 digits.
    According to documentation `std::to_chars` must not append leading zeros:
    https://en.cppreference.com/w/cpp/utility/to_chars

    Changeset should not affect `std::to_chars` performance:
    http://quick-bench.com/CEpRs14xxA9WLvkXFtaJ3TWOVAg

    Unit test that `std::from_chars` supports compatibility for both `std::to_chars` outputs (previous and fixed one) already exists:
    https://github.com/llvm-mirror/libcxx/blob/1f60111b597e5cb80a4513ec86f79b7e137f7793/test/std/utilities/charconv/charconv.from.chars/integral.pass.cpp#L63

    Reviewers: lichray, mclow.lists, ldionne, EricWF

    Reviewed By: lichray, mclow.lists

    Subscribers: zoecarver, christof, dexonsmith, libcxx-commits

    Differential Revision: https://reviews.llvm.org/D63047 (detail/ViewSVN)
    by lichray
  15. [docs] Add 'git llvm revert' to getting started guide

    Summary: This documents `git llvm revert rNNNNNN` in the getting started guide for broader visibility.

    Reviewers: jyknight, mehdi_amini

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D63023 (detail/ViewSVN)
    by rupprecht
  16. [X86] Attempt to make the Intel core CPU inheritance a little more readable and maintainable

    The recently added cooperlake CPU has made our already ugly switch statement even worse. There's a CPU exclusion list around the bf16 feature in the cooper lake block. I worry that we'll have to keep adding new CPUs to that until bf16 intercepts a client space CPU. We have several other exclusion lists in other parts of the switch due to skylakeserver, cascadelake, and cooperlake not having sgx. Another for cannonlake not having clwb but having all other features from skx.

    This removes all these special ifs at the cost of some duplication of features and a goto. I've copied all of the skx features into either cannonlake or icelakeclient(for clwb). And pulled sklyakeserver, cascadelake, and cooperlake out of the main inheritance chain into their own chain. At the end of skylakeserver we merge back into the main chain at skylakeclient but below sgx. I think this is at least easier to follow.

    Differential Revision: https://reviews.llvm.org/D63018 (detail/ViewSVN)
    by ctopper
  17. [llvm-mca] Enable bottleneck analysis when flag -all-views is specified.

    Bottleneck Analysis is one of the many views available in llvm-mca. Therefore,
    it should be enabled when flag -all-views is passed in input to the tool. (detail/ViewSVN)
    by adibiagio
  18. [FastISel] Skip creating unnecessary vregs for arguments

    This behavior was added in r130928 for both FastISel and SD, and then
    disabled in r131156 for FastISel.

    This re-enables it for FastISel with the corresponding fix.

    This is triggered only when FastISel can't lower the arguments and falls
    back to SelectionDAG for it.

    FastISel contains a map of "register fixups" where at the end of the
    selection phase it replaces all uses of a register with another
    register that FastISel sometimes pre-assigned. Code at the end of
    SelectionDAGISel::runOnMachineFunction is doing the replacement at the
    very end of the function, while other pieces that come in before that
    look through the MachineFunction and assume everything is done. In this
    case, the real issue is that the code emitting COPY instructions for the
    liveins (physreg to vreg) (EmitLiveInCopies) is checking if the vreg
    assigned to the physreg is used, and if it's not, it will skip the COPY.
    If a register wasn't replaced with its assigned fixup yet, the copy will
    be skipped and we'll end up with uses of undefined registers.

    This fix moves the replacement of registers before the emission of
    copies for the live-ins.

    The initial motivation for this fix is to enable tail calls for
    swiftself functions, which were blocked because we couldn't prove that
    the swiftself argument (which is callee-save) comes from a function
    argument (live-in), because there was an extra copy (vreg to vreg).

    A few tests are affected by this:

    * llvm/test/CodeGen/AArch64/swifterror.ll: we used to spill x21
    (callee-save) but never reload it because it's attached to the return.
    We now don't even spill it anymore.
    * llvm/test/CodeGen/*/swiftself.ll: we tail-call now.
    * llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll: I believe this
    test was not really testing the right thing, but it worked because the
    same registers were re-used.
    * llvm/test/CodeGen/ARM/cmpxchg-O0.ll: regalloc changes
    * llvm/test/CodeGen/ARM/swifterror.ll: get rid of a copy
    * llvm/test/CodeGen/Mips/*: get rid of spills and copies
    * llvm/test/CodeGen/SystemZ/swift-return.ll: smaller stack
    * llvm/test/CodeGen/X86/atomic-unordered.ll: smaller stack
    * llvm/test/CodeGen/X86/swifterror.ll: same as AArch64
    * llvm/test/DebugInfo/X86/dbg-declare-arg.ll: stack size changed

    Differential Revision: https://reviews.llvm.org/D62361 (detail/ViewSVN)
    by thegameg
  19. [scudo][standalone] Introduce the thread specific data structures

    Summary:
    This CL adds the structures dealing with thread specific data for the
    allocator. This includes the thread specific data structure itself and
    two registries for said structures: an exclusive one, where each thread
    will have its own TSD struct, and a shared one, where a pool of TSD
    structs will be shared by all threads, with dynamic reassignment at
    runtime based on contention.

    This departs from the current Scudo implementation: we intend to make
    the Registry a template parameter of the allocator (as opposed to a
    single global entity), allowing various allocators to coexist with
    different TSD registry models. As a result, TSD registry and Allocator
    are tightly coupled.

    This also corrects a couple of things in other files that I noticed
    while adding this.

    Reviewers: eugenis, vitalybuka, morehouse, hctim

    Reviewed By: morehouse

    Subscribers: srhines, mgorny, delcypher, jfb, #sanitizers, llvm-commits

    Tags: #llvm, #sanitizers

    Differential Revision: https://reviews.llvm.org/D62258 (detail/ViewSVN)
    by cryptoad
  20. [WebAssembly] Cleanup toolchain test files. NFC.

    Summary: Split up long lines to improve test readability.

    Subscribers: dschuff, jgravelle-google, aheejin, sunfish, jfb, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D63081 (detail/ViewSVN)
    by sbc
  21. [ExecutionEngine] Fix rL362941: Add UnaryOperator visitor to the interpreter

    Missed break statements. This was D62881. (detail/ViewSVN)
    by mcinally
  22. [AMDGPU] Optimize image_[load|store]_mip

    Summary:
    Replace image_load_mip/image_store_mip
    with image_load/image_store if lod is 0.

    Reviewers: arsenm, nhaehnle

    Reviewed By: arsenm

    Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D63073 (detail/ViewSVN)
    by Piotr Sobczak
  23. Revert rL362953 and its followup rL362955.

    These caused a build failure because I managed not to notice they
    depended on a later unpushed commit in my current stack. Sorry about
    that. (detail/ViewSVN)
    by statham
  24. [ARM] Add the non-MVE instructions in Arm v8.1-M.

    This should have been part of r362953, but I had a finger-trouble
    incident and committed the old rather than new version of the patch.
    Sorry. (detail/ViewSVN)
    by statham
  25. [InstCombine] allow unordered preds when canonicalizing to fabs()

    We have a known-never-nan value via 'nnan', so an unordered predicate
    is the same as its ordered sibling.

    Similar to:
    rL362937 (detail/ViewSVN)
    by spatel
  26. [ARM] Add the non-MVE instructions in Arm v8.1-M.

    This adds support for the new family of conditional selection /
    increment / negation instructions; the low-overhead branch
    instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole
    list of registers at once; the new VMRS/VMSR and VLDR/VSTR
    instructions to get data in and out of 8.1-M system registers,
    particularly including the new VPR register used by MVE vector
    predication.

    To support this, we also add a register name 'zr' (used by the CSEL
    family to force one of the inputs to the constant 0), and operand
    types for lists of registers that are also allowed to include APSR or
    VPR (used by CLRM). The VLDR/VSTR instructions also need some new
    addressing modes.

    The low-overhead branch instructions exist in their own separate
    architecture extension, which we treat as enabled by default, but you
    can say -mattr=-lob or equivalent to turn it off.

    Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover

    Reviewed By: samparker

    Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D62667 (detail/ViewSVN)
    by statham
  27. [DA] Add an option to control delinearization validity checks

    Summary: Dependence Analysis performs static checks to confirm validity
    of delinearization. These checks often fail for 64-bit targets due to
    type conversions and integer wrapping that prevent simplification of the
    SCEV expressions. These checks would also fail at compile-time if the
    lower bound of the loops are compile-time unknown.
    Author: bmahjour
    Reviewer: Meinersbur, jdoerfert, kbarton, dmgreen, fhahn
    Reviewed By: Meinersbur, jdoerfert, dmgreen
    Subscribers: fhahn, hiraditya, javed.absar, llvm-commits, Whitney,
    etiotto
    Tag: LLVM
    Differential Revision: https://reviews.llvm.org/D62610 (detail/ViewSVN)
    by whitneyt
  28. [DebugInfo] Terminate all location-lists at end of block

    This commit reapplies r359426 (which was reverted in r360301 due to
    performance problems) and rolls in D61940 to address the performance problem.
    I've combined the two to avoid creating a span of slow-performance, and to
    ease reverting if more problems crop up.

    The summary of D61940: This patch removes the "ChangingRegs" facility in
    DbgEntityHistoryCalculator, as its overapproximate nature can produce incorrect
    variable locations. An unchanging register doesn't mean a variable doesn't
    change its location.

    The patch kills off everything that calculates the ChangingRegs vector.
    Previously ChangingRegs spotted epilogues and marked registers as unchanging if
    they weren't modified outside the epilogue, increasing the chance that we can
    emit a single-location variable record. Without this feature,
    debug-loc-offset.mir and pr19307.mir become temporarily XFAIL. They'll be
    re-enabled by D62314, using the FrameDestroy flag to identify epilogues, I've
    split this into two steps as FrameDestroy isn't necessarily supported by all
    backends.

    The logic for terminating variable locations at the end of a basic block now
    becomes much more enjoyably simple: we just terminate them all.

    Other test changes: inlined-argument.ll becomes XFAIL, but for a longer term.
    The current algorithm for detecting that a variable has a single-location
    doesn't work in this scenario (inlined function in multiple blocks), only other
    bugs were making this test work. fission-ranges.ll gets slightly refreshed too,
    as the location of "p" is now correctly determined to be a single location.

    Differential Revision: https://reviews.llvm.org/D61940 (detail/ViewSVN)
    by jmorse
  29. Re-land "[CodeComplete] Improve overload handling for C++ qualified and ref-qualified methods."

    ShadowMapEntry is now really, truly a normal class. (detail/ViewSVN)
    by sammccall
  30. [InstCombine] add tests for fabs() with unordered preds; NFC (detail/ViewSVN)
    by spatel
  31. [IRBuilder] Add CreateFNegFMF(...) to the IRBuilder

    Differential Revision: https://reviews.llvm.org/D62521 (detail/ViewSVN)
    by mcinally
  32. [InstCombine] fix bug in canonicalization to fabs()

    Forgot to translate the predicate clauses in rL362943. (detail/ViewSVN)
    by spatel
  33. Revert "[CodeComplete] Improve overload handling for C++ qualified and ref-qualified methods."

    This reverts commit r362924, which causes a double-free of ShadowMapEntry. (detail/ViewSVN)
    by sammccall
  34. [InstCombine] change canonicalization to fabs() to use FMF on fsub

    Similar to rL362909:
    This isn't the ideal fix (use FMF on the select), but it's still an
    improvement until we have better FMF propagation to selects and other
    FP math operators.

    I don't think there's much risk of regression from this change by
    not including the FMF on the fcmp any more. The nsz/nnan FMF
    should be the same on the fcmp and the fsub because they have the
    same operand. (detail/ViewSVN)
    by spatel
  35. [ARM] Disallow PC, and optionally SP, in VMOVRH and VMOVHR.

    Arm v8.1-M supports the VMOV instructions that move a half-precision
    value to and from a GPR, but not if the GPR is SP or PC.

    To fix this, I've changed those instructions to use the rGPR register
    class instead of GPR. rGPR always excludes PC, and it excludes SP
    except in the presence of the HasV8Ops target feature (i.e. Arm v8-A).
    So the effect is that VMOV.F16 to and from PC is now illegal
    everywhere, but VMOV.F16 to and from SP is illegal only on non-v8-A
    cores (which I believe is all as it should be).

    Reviewers: dmgreen, samparker, SjoerdMeijer, ostannard

    Reviewed By: ostannard

    Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D60704 (detail/ViewSVN)
    by statham
  36. [ExecutionEngine] Add UnaryOperator visitor to the interpreter

    This is to support the unary FNeg instruction.

    Differential Revision: https://reviews.llvm.org/D62881 (detail/ViewSVN)
    by mcinally
  37. [yaml2obj] - Remove TODOs from dynsymtab-implicit-sections-size-content.yaml. NFCI.

    Now when https://bugs.llvm.org/show_bug.cgi?id=42215 is fixed,
    we can remove these TODOs. (detail/ViewSVN)
    by grimar
  38. [clangd] Revamp textDocument/onTypeFormatting.

    Summary:
    The existing implementation (which triggers on }) is fairly simple and
    has flaws:
    - doesn't trigger frequently/regularly enough (particularly in editors that type the }
    for you)
    - often reformats too much code around the edit
    - has jarring cases that I don't have clear ideas for fixing

    This implementation is designed to trigger on newline, which feels to me more
    intuitive than } or ;.
    It does have allow for reformatting after other characters - it has a
    basic behavior and a model for adding specialized behavior for
    particular characters. But at least initially I'd stick to advertising
    \n in the capabilities.

    This also handles comment splitting: when you insert a line break inside
    a line comment, it will make the new line into an aligned line comment.

    Working on tests, but want people to patch it in and try it - it's hard to
    see if "feel" is right purely by looking at a test.

    Reviewers: ilya-biryukov, hokein

    Subscribers: mgorny, ioeric, MaskRay, jkorous, arphaman, kadircet, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D60605 (detail/ViewSVN)
    by sammccall
  39. [llvm-readobj/llvm-readelf] - Don't fail to dump the object if .dynsym has broken sh_link field.

    This is https://bugs.llvm.org/show_bug.cgi?id=42215.

    GNU readelf allows to dump the objects in that case,
    but llvm-readobj/llvm-readelf reports an error and stops.

    The patch fixes that.

    Differential revision: https://reviews.llvm.org/D63074 (detail/ViewSVN)
    by grimar
  40. [InstCombine] allow unordered preds when canonicalizing to fabs()

    PR42179:
    https://bugs.llvm.org/show_bug.cgi?id=42179 (detail/ViewSVN)
    by spatel
  41. [InstCombine] add tests for fcmp unordered pred -> fabs (PR42179); NFC (detail/ViewSVN)
    by spatel
  42. [MCA] Fix -Wunused-private-field warning after r362933. NFC

    This should unbreak the buildbots. (detail/ViewSVN)
    by adibiagio
  43. [clangd] Stop marshalling/requiring FormattingOptions. We never did anything with them. (detail/ViewSVN)
    by sammccall
  44. [MCA] Further refactor the bottleneck analysis view. NFCI. (detail/ViewSVN)
    by adibiagio
  45. gn build: Merge r362913 (detail/ViewSVN)
    by nico
  46. [yaml2obj/obj2yaml] - Make RawContentSection::Content and RawContentSection::Size optional

    This is a follow-up for D62809.

    Content and Size fields should be optional as was discussed in comments
    of the D62809's thread. With that, we can describe a specific string table and
    symbol table sections in a more correct way and also show appropriate errors.

    The patch adds lots of test cases where the behavior is described in details.

    Differential revision: https://reviews.llvm.org/D62957 (detail/ViewSVN)
    by grimar

Started by upstream project clang-stage2-Rthinlto_relay build number 1593
originally caused by:

This run spent:

  • 6 ms waiting;
  • 6 hr 7 min build duration;
  • 6 hr 7 min total from scheduled to completion.
Cobol Warnings: 0 warnings.
  • No warnings since build 10,378.
  • New zero warnings highscore: no warnings for 377 days!
Test Result (no failures)