Started 2 days 21 hr ago
Took 48 min on green-dragon-19

Failed Build #18205 (Jun 14, 2019 3:21:25 AM)

  • : 363355
  • : 363352
  • : 363327
  • : 362745
  • : 363333
  • : 363296
  1. Move commentary on opcode translation for code16 mov instructions
    to segment registers closer to the segment register check for when
    we add further optimizations. (detail/ViewSVN)
    by echristo
  2. [llvm-objcopy] Remove no-op flush of errs

    Reviewers: alexshap, rupprecht, jhenderson

    Subscribers: jakehehrlich, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by abrachet
  3. gn build: Merge r363204 (clang-scan-deps) (detail/ViewSVN)
    by nico
  4. Revert 363295, it caused PR42276. Also revert follow-ups 363337, 363340.

    Revert 363340 "Remove unused SK_LValueToRValue initialization step."
    Revert 363337 "PR23833, DR2140: an lvalue-to-rvalue conversion on a glvalue of type"
    Revert 363295 "C++ DR712 and others: handle non-odr-use resulting from an lvalue-to-rvalue conversion applied to a member access or similar not-quite-trivial lvalue expression." (detail/ViewSVN)
    by nico
  5. [llvm-objcopy] Changed command line parsing errors

    Summary: Tidied up errors during command line parsing to be more consistent with the rest of llvm-objcopy errors.

    Reviewers: jhenderson, rupprecht, espindola, alexshap

    Reviewed By: jhenderson, rupprecht

    Subscribers: emaste, arichardson, MaskRay, llvm-commits, jakehehrlich

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by abrachet
  6. DebugInfo: Include enumerators in pubnames

    This is consistent with GCC's behavior (which is the defacto standard
    for pubnames). Though I find the presence of enumerators from enum
    classes to be a bit confusing, possibly a bug on GCC's end (since they
    can't be named unqualified, unlike the other names - and names nested in
    classes don't go in pubnames, for instance - presumably because one must
    name the class first & that's enough to limit the scope of the search) (detail/ViewSVN)
    by dblaikie
  7. [X86] Add target triple for live-debug-values-fragments.mir (detail/ViewSVN)
    by timshen
  8. Add REQUIRES: zlib to test added in r363325 as the profile uses zlib compression. (detail/ViewSVN)
    by dyung
  9. [Targets] Move soft-float-abi filtering to `initFeatureMap`

    ARM has a special target feature called soft-float-abi. This feature is
    special, since we get it passed to us explicitly in the frontend, but
    filter it out before it can land in any target feature strings in LLVM

    __attribute__((target(""))) doesn't quite filter these features out
    properly, so today, we get warnings about soft-float-abi being an
    unknown feature from the backend.

    This CL has us filter soft-float-abi out at a slightly different point,
    so we don't end up passing these invalid features to the backend.

    Differential Revision: (detail/ViewSVN)
    by George Burgess IV
  10. [AMDGPU] gfx1011/gfx1012 clang support

    Differential Revision: (detail/ViewSVN)
    by rampitec
  11. [AMDGPU] gfx1011/gfx1012 targets

    Differential Revision: (detail/ViewSVN)
    by rampitec
  12. Revert "[Remarks] Refactor optimization remarks setup"

    This reverts commit 6e6e3af55bb97e1a4c97375c15a2b0099120c5a7.

    This breaks greendragon. (detail/ViewSVN)
    by thegameg
  13. [Coverage] Speculative fix for r363325 for an older compiler

    It looks like an older version of gcc can't figure out that it needs to
    move a unique_ptr while implicitly constructing an Expected object. (detail/ViewSVN)
    by Vedant Kumar
  14. [AMDGPU] gfx1010 wave32 clang support

    Differential Revision: (detail/ViewSVN)
    by rampitec
  15. Remove unused SK_LValueToRValue initialization step.

    In addition to being unused and duplicating code, this was also wrong
    (it didn't properly mark the operand as being potentially not odr-used). (detail/ViewSVN)
    by rsmith
  16. [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32

    Differential Revision: (detail/ViewSVN)
    by rampitec
  17. PR23833, DR2140: an lvalue-to-rvalue conversion on a glvalue of type
    nullptr_t does not access memory.

    We now reuse CK_NullToPointer to represent a conversion from a glvalue
    of type nullptr_t to a prvalue of nullptr_t where necessary.

    This reinstates r345562, reverted in r346065, now that CodeGen's
    handling of non-odr-used variables has been fixed. (detail/ViewSVN)
    by rsmith
  18. [llvm-objcopy] Fix sparc target endianness

    Summary: AFAIK, the "sparc" target is big endian and the target for 32-bit little-endian SPARC is denoted as "sparcel". This patch fixes the endianness of "sparc" target and adds "sparcel" target for 32-bit little-endian SPARC.

    Reviewers: espindola, alexshap, rupprecht, jhenderson

    Reviewed By: jhenderson

    Subscribers: jyknight, emaste, arichardson, fedor.sergeev, jakehehrlich, MaskRay, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by seiya
  19. Use fully qualified name when printing S_CONSTANT records

    Before it was using the fully qualified name only for static data members.
    Now it does for all variable names to match MSVC.

    Reviewers: rnk

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by akhuang
  20. Symbolize: Remove dead code. NFCI.

    The only caller of SymbolizableObjectFile::create passes a non-null
    DebugInfoContext and asserts that they do so. Move the assert into
    SymbolizableObjectFile::create and remove null checks.

    Differential Revision: (detail/ViewSVN)
    by pcc
  21. [libc++] Fix build with gcc 4.8

    gcc 4.8.4 (but not 5.4.0 or 7.3.0) has trouble initializing errc with {}, giving
    the error in [1]. This CL switches to explicitly using errc(0), which gcc 4.8


    Differential Revision: (detail/ViewSVN)
    by thomasanderson
  22. [AMDGPU] gfx10 documentation update. NFC. (detail/ViewSVN)
    by rampitec
  23. [GlobalISel][IRTranslator] Add debug loc with line 0 to constants emitted into the entry block.

    Constants, including G_GLOBAL_VALUE, are all emitted into the entry block which
    lets us use the vreg def assuming it dominates all other users. However, it can
    cause jumpy debug behaviour since the DebugLoc attached to these MIs are from
    a user instruction that could be in a different block.

    Fixes PR40887.

    Differential Revision: (detail/ViewSVN)
    by aemerson
  24. [X86Disassembler] Unify the EVEX and VEX code in emitContextTable. Merge the ATTR_VEXL/ATTR_EVEXL bits. NFCI

    Merging the two bits shrinks the context table from 16384 bytes to 8192 bytes.

    Remove the ATTRIBUTE_BITS macro and just create an enum directly. Then fix the ATTR_max define to be 8192 to reflect the table size so we stop hardcoding it separately. (detail/ViewSVN)
    by ctopper
  25. [MachinePiepliner] Don't check boundary node in checkValidNodeOrder

    This was exposed by PowerPC target enablement.

    In ScheduleDAG, if we haven't seen any uses in this scheduling region,
    we will create a dependence edge to ExitSU to model the live-out latency.
    This is required for vreg defs with no in-region use, and prefetches with
    no vreg def.

    When we build NodeOrder in Scheduler, we ignore these boundary nodes.
    However, when we check Succs in checkValidNodeOrder, we did not skip
    them, so we still assume all the nodes have been sorted and in order in
    Indices array. So when we call lower_bound() for ExitSU, it will return
    Indices.end(), causing memory issues in following Node access.

    Differential Revision: (detail/ViewSVN)
    by jsji
  26. [Remarks] Refactor optimization remarks setup

    * Add a common function to setup opt-remarks
    * Rename common options to the same names
    * Add error types to distinguish between file errors and regex errors (detail/ViewSVN)
    by thegameg
  27. fix whitespaces (detail/ViewSVN)
    by kcc
  28. [libFuzzer] simplify the DFT trace collection using the new faster DFSan mode that traces up to 16 labels at a time and never runs out of labels. (detail/ViewSVN)
    by kcc
  29. [Coverage] Load code coverage data from archives

    Support loading code coverage data from regular archives, thin archives,
    and from MachO universal binaries which contain archives.

    Testing: check-llvm, check-profile (with {A,UB}San enabled)


    Differential Revision: (detail/ViewSVN)
    by Vedant Kumar
  30. gn build: Merge r363242 (detail/ViewSVN)
    by nico
  31. [AMDGPU] gfx1010 AMDGPUSetCCOp definition

    It was missing from D63293 and breaks in a debug tablegen w/o
    this part. (detail/ViewSVN)
    by rampitec
  32. [ORC] Rename MaterializationResponsibility resolve and emit methods to

    The 'notify' prefix better describes what these methods do: they update the JIT
    symbol states and notify any pending queries that the 'resolved' and 'emitted'
    states have been reached (rather than actually performing the resolution or
    emission themselves). Since new states are going to be introduced in the near
    future (to track symbol registration/initialization) it's worth changing the
    convention pre-emptively to avoid further confusion. (detail/ViewSVN)
    by Lang Hames
  33. [dfsan] Introduce dfsan_flush().

    dfsan_flush() allows to restart tain tracking from scratch in the same process.
    The primary purpose right now is to allow more efficient data flow tracing
    for DFT fuzzing:

    Reviewers: pcc

    Reviewed By: pcc

    Subscribers: delcypher, #sanitizers, llvm-commits

    Tags: #llvm, #sanitizers

    Differential Revision: (detail/ViewSVN)
    by kcc
  34. [LangRef] Clarify poison semantics

    I find the current documentation of poison somewhat confusing,
    mainly because its use of "undefined behavior" doesn't seem to
    align with our usual interpretation (of immediate UB). Especially
    the sentence "any instruction that has a dependence on a poison
    value has undefined behavior" is very confusing.

    Clarify poison semantics by:

    * Replacing the introductory paragraph with the standard rationale
       for having poison values.
    * Spelling out that instructions depending on poison return poison.
    * Spelling out how we go from a poison value to immediate undefined
       behavior and give the two examples we currently use in ValueTracking.
    * Spelling out that side effects depending on poison are UB.

    Differential Revision: (detail/ViewSVN)
    by nikic
  35. [SimplifyCFG] NFC, update Switch tests as a baseline.

    Also add baseline tests to show effect of later patches.

    There were a couple of regressions here that were never caught,
    but my patch set that this is a preparation to will fix them.

    This is the third attempt to land this patch.

    Differential Revision: (detail/ViewSVN)
    by shawnl
  36. Add a clarifying comment about branching on poison

    I recently got this wrong (again), and I'm sure I'm not the only one.  Put a comment in the logical place someone would look to "fix" the obvious "missed optimization" which arrises based on the common misunderstanding.  Hopefully, this will save others time.  :) (detail/ViewSVN)
    by reames
  37. Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"

    This reverts commit 1d85a7518c6b660a85caabd580b632f9abd5a8ab. (detail/ViewSVN)
    by mcinally
  38. Revert "[NFC][CodeGen] Add unary fneg tests to fmul-combines.ll fnabs.ll"

    This reverts commit 5c0114058126757ce21e546997121afffc8119cd. (detail/ViewSVN)
    by mcinally
  39. Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma_patterns_wide.ll"

    This reverts commit f1b8c6ac4f9d31899a2bc128f8a37b5a1c3e1f77. (detail/ViewSVN)
    by mcinally
  40. Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma_patterns.ll"

    This reverts commit 06de52674da73f30751f3ff19fdf457f87077c65. (detail/ViewSVN)
    by mcinally
  41. Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma4-fneg-combine.ll"

    This reverts commit f288a0685f874d2b965db25a16b9c44f78c55b12. (detail/ViewSVN)
    by mcinally
  42. Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-scalar-combine.ll"

    This reverts commit 3d2ee0053aa2576fd19cd169798c496199f0a29b. (detail/ViewSVN)
    by mcinally
  43. Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-intrinsics-x86.ll"

    This reverts commit 169fc2b0209d5574fca0927a707706ea2d5f5a09. (detail/ViewSVN)
    by mcinally
  44. Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma4-intrinsics-x86.ll"

    This reverts commit 66f286845cad73a280617a606e29c9009bb4da87. (detail/ViewSVN)
    by mcinally
  45. Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."

    This reverts commit 4f3cf3853e1145e3e08fb42ace79ba3e4e268540. (detail/ViewSVN)
    by mcinally
  46. Revert "[NFC][CodeGen] Add unary FNeg tests to X86/fma-intrinsics-canonical.ll"

    This reverts commit ee5881a88cbe148bb64d14b8a5b31a314ee22343. (detail/ViewSVN)
    by mcinally
  47. Revert "[NFC][CodeGen] Forgot 2 unary FNeg tests in X86/fma-intrinsics-canonical.ll"

    This reverts commit 5f39a3096f8e7b09bd1645f4e4ca66343066a6e1. (detail/ViewSVN)
    by mcinally
  48. Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-fneg-combine.ll"

    This reverts commit 10c085554215e84831d272f2e6a93b7c70d143bf. (detail/ViewSVN)
    by mcinally
  49. Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"

    This reverts commit e04c4b6af81d6142c4ff8dd9d00f44a27e9a66eb. (detail/ViewSVN)
    by mcinally
  50. Revert "[NFC][CodeGen] Add unary FNeg tests to X86/avx512vl-intrinsics-fast-isel.ll X86/combine-fabs.ll"

    This reverts commit 6fe46ec25d849a9fd5be25acf0ee77e3c06c0786. (detail/ViewSVN)
    by mcinally
  51. Revert "[NFC][CodeGen] Add unary FNeg tests to X86/avx512vl-intrinsics-fast-isel.ll"

    This reverts commit 2aa5ada267d268fec2b1e90efeae1ddee24617be. (detail/ViewSVN)
    by mcinally
  52. Revert "[NFC][CodeGen] Add unary FNeg tests to X86/avx512vl-intrinsics-fast-isel.ll"

    This reverts commit 27a5db9de57d13d44c7a7704e06d8ba69ec8b4af. (detail/ViewSVN)
    by mcinally
  53. Revert "[NFC][CodeGen] Add unary FNeg tests to X86/avx512-intrinsics-fast-isel.ll"

    This reverts commit 41e0b9f2803089155536bdec7cbea6b82680a727. (detail/ViewSVN)
    by mcinally
  54. Revert "[NFC][CodeGen] Add unary FNeg tests to X86/avx512-intrinsics-fast-isel.ll"

    This reverts commit aeb89f8b33d8fca4e819ba41267093699a7e4885. (detail/ViewSVN)
    by mcinally
  55. [AMDGPU] gfx1010 base changes for wave32

    Differential Revision: (detail/ViewSVN)
    by rampitec
  56. [lit] Disable test on darwin when building shared libs.

    This test fails to link shared libraries because tries to run
    a copied version of clang-check to see if the mock version of libcxx
    in the same directory can be loaded dynamically.  Since the test is
    specifically designed not to look in the default just-built lib
    directory, it must be disabled when building with

    Currently only disabling it on Darwin and basing it on the
    enable_shared flag.

    Reviewed By: ilya-biryukov

    Tags: #clang, #llvm

    Differential Revision: (detail/ViewSVN)
    by dhinton
  57. [AMDGPU] gfx1010: small test change for wave32. NFC (detail/ViewSVN)
    by rampitec
  58. [clang-tidy] Make ClangTidyCheck::OptionsView public.

    Summary: The `OptionsView` class is currently protected. This constraint prevents tidies from passing the OptionsView to, for example, a helper function. Similarly, TransformerClangTidyCheck cannot pass the `OptionsView` object to functions that generate `tooling::RewriteRule`s.  The latter is needed to allow the definition of such rules to depend on the clang-tidy options, as demonstrated in the child revision.

    Reviewers: gribozavr

    Subscribers: xazax.hun, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by ymandel
  59. C++ DR712 and others: handle non-odr-use resulting from an lvalue-to-rvalue conversion applied to a member access or similar not-quite-trivial lvalue expression.

    When a variable is named in a context where we can't directly emit a
    reference to it (because we don't know for sure that it's going to be
    defined, or it's from an enclosing function and not captured, or the
    reference might not "work" for some reason), we emit a copy of the
    variable as a global and use that for the known-to-be-read-only access.

    Reviewers: rjmccall

    Subscribers: jdoerfert, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by rsmith
  60. [docs] Fix TableGen/LangRef typos

    This fixes:
    - `Pred` -> `Prep`
    - `IfDef` -> `Ifdef` (rst is case sensitive here) (detail/ViewSVN)
    by rupprecht
  61. [LFTR] Rename variable to minimize confusion [NFC]

    As pointed out by Nikita in D62625, BackedgeTakenCount is generally used to refer to the backedge taken count of the loop.  A conditional backedge taken count - one which only applies if a particular exit is taken - is called a ExitCount in SCEV code, so be consistent here. (detail/ViewSVN)
    by reames
  62. [LFTR] Stylistic cleanup as suggested in last review comment of D62939 [NFC] (detail/ViewSVN)
    by reames
  63. [InstCombine] add test for failed libfunction prototype matching; NFC (detail/ViewSVN)
    by spatel
  64. [libc++] Add missing #include in <cwchar> tests

    Thanks to Mikhail Maltsev for the patch.
    Differential Revision: (detail/ViewSVN)
    by Louis Dionne
  65. Fix a bug w/inbounds invalidation in LFTR

    This contains fixes for two cases where we might invalidate inbounds and leave it stale in the IR (a miscompile). Case 1 is when switching to an IV with no dynamically live uses, and case 2 is when doing pre-to-post conversion on the same pointer type IV.

    The basic scheme used is to prove that using the given IV (pre or post increment forms) would have to already trigger UB on the path to the test we're modifying.  As such, our potential UB triggering use does not change the semantics of the original program.

    As was pointed out in the review thread by Nikita, this is defending against a separate issue from the hasConcreteDef case. This is about poison, that's about undef. Unfortunately, the two are different, see Nikita's comment for a fuller explanation, he explains it well.

    (Note: I'm going to address Nikita's last style comment in a separate commit just to minimize chance of subtle bugs being introduced due to typos.)

    Differential Revision: (detail/ViewSVN)
    by reames
  66. PR42182: Allow thread-local to use __cxa_thread_atexit when
    -fno-use-cxx-atexit is used

    This matches the GCC behavior, __cxa_thread_atexit should be permissible
    even though cxa_atexit is disabled.

    Differential Revision: (detail/ViewSVN)
    by erichkeane
  67. [clang][NewPM] Fix broken -O0 test from missing assumptions

    Add an AssumptionCache callback to the InlineFuntionInfo used for the
    AlwaysInlinerPass to match codegen of the AlwaysInlinerLegacyPass to generate
    llvm.assume. This fixes CodeGen/builtin-movdir.c when new PM is enabled by

    Differential Revision: (detail/ViewSVN)
    by leonardchan
  68. [InstCombine] auto-generate complete test checks; NFC (detail/ViewSVN)
    by spatel
  69. [NFC] Updated testcase for D54411/rL363284 (detail/ViewSVN)
    by xbolva00
  70. [Codegen] Merge tail blocks with no successors after block placement

    I found the following case having tail blocks with no successors merging opportunities after block placement.

    Before block placement:

        bne a0, 0, bb2:

        mv a0, 1


        mv a0, 1

        mv a0, -1

    The conditional branch bne in bb0 is opposite to beq.

    After block placement:

        beq a0, 0, bb1


        mv a0, -1

        mv a0, 1

        mv a0, 1

    After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.

    Author of original patch: Jim Lin

    Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen

    Reviewed By: Jim, dmgreen

    Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by xbolva00
  71. [clang][NewPM] Fix split debug test

    This contains the part of D62225 which fixes CodeGen/split-debug-single-file.c
    by not placing .dwo sections when using -enable-split-dwarf=split.

    Differential Revision: (detail/ViewSVN)
    by leonardchan
  72. [clang][NewPM] Fix broken profile test

    This contains the part of D62225 which fixes Profile/gcc-flag-compatibility.c
    by adding the pass that allows default profile generation to work under the new
    PM. It seems that ./default.profraw was not being generated with new PM enabled.

    Differential Revision: (detail/ViewSVN)
    by leonardchan
  73. [clang][NewPM] Fix broken -O0 test from the AlwaysInliner

    This contains the part of D62225 which prevents insertion of lifetime
    intrinsics when creating the AlwaysInliner. This fixes the following tests
    when the new PM is enabled by default:

    Clang :: CodeGen/aarch64-neon-across.c
    Clang :: CodeGen/aarch64-neon-fcvt-intrinsics.c
    Clang :: CodeGen/aarch64-neon-fma.c
    Clang :: CodeGen/aarch64-neon-perm.c
    Clang :: CodeGen/aarch64-neon-tbl.c
    Clang :: CodeGen/aarch64-poly128.c
    Clang :: CodeGen/aarch64-v8.2a-neon-intrinsics.c
    Clang :: CodeGen/arm-neon-fma.c
    Clang :: CodeGen/arm-neon-numeric-maxmin.c
    Clang :: CodeGen/arm-neon-vcvtX.c
    Clang :: CodeGen/avx-builtins.c
    Clang :: CodeGen/builtins-ppc-p9vector.c
    Clang :: CodeGen/builtins-ppc-vsx.c
    Clang :: CodeGen/lifetime.c
    Clang :: CodeGen/sse-builtins.c
    Clang :: CodeGen/sse2-builtins.c

    Differential Revision: (detail/ViewSVN)
    by leonardchan
  74. [AMDGPU] ImmArg and SourceOfDivergence for permlane/dpp

    Added missing ImmArg and SourceOfDivergence to the crosslane

    Differential Revision: (detail/ViewSVN)
    by rampitec
  75. [NFC][CodeGen] Add unary FNeg tests to X86/avx512-intrinsics-fast-isel.ll

    Patch 2 of n. (detail/ViewSVN)
    by mcinally
  76. [EarlyCSE] Ensure equal keys have the same hash value

    The logic in EarlyCSE that looks through 'not' operations in the
    predicate recognizes e.g. that `select (not (cmp sgt X, Y)), X, Y` is
    equivalent to `select (cmp sgt X, Y), Y, X`.  Without this change,
    however, only the latter is recognized as a form of `smin X, Y`, so the
    two expressions receive different hash codes.  This leads to missed
    optimization opportunities when the quadratic probing for the two hashes
    doesn't happen to collide, and assertion failures when probing doesn't
    collide on insertion but does collide on a subsequent table grow

    This change inverts the order of some of the pattern matching, checking
    first for the optional `not` and then for the min/max/abs patterns, so
    that e.g. both expressions above are recognized as a form of `smin X, Y`.

    It also adds an assertion to isEqual verifying that it implies equal
    hash codes; this fires when there's a collision during insertion, not
    just grow, and so will make it easier to notice if these functions fall
    out of sync again.  A new flag --earlycse-debug-hash is added which can
    be used when changing the hash function; it forces hash collisions so
    that any pair of values inserted which compare as equal but hash
    differently will be caught by the isEqual assertion.

    Reviewers: spatel, nikic

    Reviewed By: spatel, nikic

    Subscribers: lebedev.ri, arsenm, craig.topper, efriedma, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by josepht
  77. [clang-tidy] Made abseil-faster-strsplit-delimiter tests pass on C++17

    Reviewers: hokein, gribozavr

    Reviewed By: hokein, gribozavr

    Subscribers: xazax.hun, cfe-commits

    Tags: #clang

    Differential Revision:

    Patch by Johan Vikström. (detail/ViewSVN)
    by gribozavr
  78. [clang-tidy] Fixed abseil-time-subtraction to work on C++17

    Summary: Fixed abseil-time-subtraction to work on C++17

    Reviewers: hokein, gribozavr

    Subscribers: xazax.hun, cfe-commits

    Tags: #clang

    Differential Revision:

    Patch by Johan Vikström. (detail/ViewSVN)
    by gribozavr
  79. [clang-tidy] Made abseil-upgrade-duration-conversions tests pass on c++17

    Summary: Made abseil-upgrade-duration-conversions tests pass on c++17

    Reviewers: hokein, gribozavr

    Reviewed By: gribozavr

    Subscribers: xazax.hun, cfe-commits

    Tags: #clang

    Differential Revision:

    Patch by Johan Vikström. (detail/ViewSVN)
    by gribozavr
  80. Fix GCC compiler warning. NFC. (detail/ViewSVN)
    by hliao
  81. [X86] Use fresh MemOps when emitting VAARG64

    Previously it copied over MachineMemOperands verbatim which caused MOV32rm to have store flags set, and MOV32mr to have load flags set. This fixes some assertions being thrown with EXPENSIVE_CHECKS on.

    Committed on behalf of @luke (Luke Lau)

    Differential Revision: (detail/ViewSVN)
    by rksimon
  82. Remove ';' after namespace's closing bracket [NFC] (detail/ViewSVN)
    by dstenb
  83. [docs][llvm-symbolizer] Fix formatting issue with --functions

    Reviewed by: rupprecht

    Differential Revision: (detail/ViewSVN)
    by jhenderson
  84. [FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack

    Relate bug:

    The shrink wrapping pass prematurally restores the stack, at a point where the stack might still be accessed.
    Taking an exception can cause the stack to be corrupted.

    As a first approach, this patch is overly conservative, assuming that any instruction that may load or store could access
    the stack.

    Reviewers: dmgreen, qcolombet

    Reviewed By: qcolombet

    Subscribers: simpal01, efriedma, eli.friedman, javed.absar, llvm-commits, eugenis, chill, carwil, thegameg

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by dnsampaio
  85. [docs][llvm-dwarfdump] Add missing options and behaviour to documentation

    This fixes

    llvm-dwarfdump's documentation was missing a number of options and other
    behaviours. This change tries to fix up the documentation by adding
    these missing items.

    Reviewed by: JDevlieghere

    Differential Revision: (detail/ViewSVN)
    by jhenderson
  86. [clang-tidy] Fixed abseil-duration-unnecessary-conversion tests for c++17

    Summary: Fixed abseil-duration-unnecessary-conversion tests for c++17

    Reviewers: hokein, gribozavr

    Reviewed By: gribozavr

    Subscribers: xazax.hun, cfe-commits

    Tags: #clang

    Differential Revision:

    Patch by Johan Vikström. (detail/ViewSVN)
    by gribozavr
  87. Added AST matcher for ignoring elidable constructors

    Summary: Added AST matcher for ignoring elidable move constructors

    Reviewers: hokein, gribozavr

    Reviewed By: hokein, gribozavr

    Subscribers: cfe-commits

    Tags: #clang

    Differential Revision:

    Patch by Johan Vikström. (detail/ViewSVN)
    by gribozavr
  88. Extra error checking to ARMAttributeParser

    The patch checks for subsection length as discussed in D63191 (detail/ViewSVN)
    by evgeny777
  89. [NFC] Sink a function call into LiveDebugValues::process

    This was requested in D62904, which I successfully missed. This is just
    a refactor and shouldn't change any behaviour. (detail/ViewSVN)
    by jmorse
  90. [ARM] Set up infrastructure for MVE vector instructions.

    This commit prepares the way to start adding the main collection of
    MVE instructions, which operate on the 128-bit vector registers.

    The most obvious thing that's needed, and the simplest, is to add the
    MQPR register class, which is like the existing QPR except that it has
    fewer registers in it.

    The more complicated part: MVE defines a system of vector predication,
    in which instructions operating on 128-bit vector registers can be
    constrained to operate on only a subset of the lanes, using a system
    of prefix instructions similar to the existing Thumb IT, in that you
    have one prefix instruction which designates up to 4 following
    instructions as subject to predication, and within that sequence, the
    predicate can be inverted by means of T/E suffixes ('Then' / 'Else').

    To support instructions of this type, we've added two new Tablegen
    classes `vpred_n` and `vpred_r` for standard clusters of MC operands
    to add to a predicated instruction. Both include a flag indicating how
    the instruction is predicated at all (options are T, E and 'not
    predicated'), and an input register field for the register controlling
    the set of active lanes. They differ from each other in that `vpred_r`
    also includes an input operand for the previous value of the output
    register, for instructions that leave inactive lanes unchanged.
    `vpred_n` lacks that extra operand; it will be used for instructions
    that don't preserve inactive lanes in their output register (either
    because inactive lanes are zeroed, as the MVE load instructions do, or
    because the output register isn't a vector at all).

    This commit also adds the family of prefix instructions themselves
    (VPT / VPST), and all the machinery needed to work with them in
    assembly and disassembly (e.g. generating the 't' and 'e' mnemonic
    suffixes on disassembled instructions within a predicated block)

    I've added a couple of demo instructions that derive from the new
    Tablegen base classes and use those two operand clusters. The bulk of
    the vector instructions will come in followup commits small enough to
    be manageable. (One exception is that I've added the full version of
    `isMnemonicVPTPredicable` in the AsmParser, because it seemed
    pointless to carefully split it up.)

    Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover

    Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by statham
  91. [CodeGen] Add getMachineMemOperand + MachineMemOperand::Flags allocator helper wrapper. NFCI.

    Pre-commit for D62726 on behalf of @luke (Luke Lau) (detail/ViewSVN)
    by rksimon
  92. [DebugInfo] Honour variable fragments in LiveDebugValues

    This patch makes the LiveDebugValues pass consider fragments when propagating
    DBG_VALUE insts between blocks, fixing PR41979. Fragment info for a variable
    location is added to the open-ranges key, which allows distinct fragments to be
    tracked separately. To handle overlapping fragments things become slightly
    funkier. To avoid excessive searching for overlaps in the data-flow part of
    LiveDebugValues, this patch:
    * Pre-computes pairings of fragments that overlap, for each DILocalVariable
    * During data-flow, whenever something happens that causes an open range to
       be terminated (via erase), any fragments pre-determined to overlap are
       also terminated.

    The effect of which is that when encountering a DBG_VALUE fragment that
    overlaps others, the overlapped fragments do not get propagated to other
    blocks. We still rely on later location-list building to correctly handle
    overlapping fragments within blocks.

    It's unclear whether a mixture of DBG_VALUEs with and without fragmented
    expressions are legitimate. To avoid suprises, this patch interprets a
    DBG_VALUE with no fragment as overlapping any DBG_VALUE _with_ a fragment.

    Differential Revision: (detail/ViewSVN)
    by jmorse
  93. [AMDGPU][MC] Enabled constant expressions as operands of s_getreg/s_setreg

    See bug 40820:

    Reviewers: artem.tamazov, arsenm

    Differential Revision: (detail/ViewSVN)
    by dpreobra
  94. [ThinLTO][Bitcode] Add 'entrycount' to FS_COMBINED_PROFILE. NFC

    Differential revision: (detail/ViewSVN)
    by evgeny777
  95. [Clangd] Fixed clangd diagnostics priority

    - Fixed diagnostics where zero width inserted ranges were being used instead of the whole token
    - Added unit tests

    Patch by @SureYeaah !

    Reviewers: sammccall, kadircet

    Reviewed By: kadircet

    Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits

    Tags: #clang-tools-extra, #clang

    Differential Revision: (detail/ViewSVN)
    by kadircet
  96. [X86][AVX] Add broadcast(v4f64 hadd) test (detail/ViewSVN)
    by rksimon
  97. [X86][SSE] Avoid assert for broadcast(horiz-op()) cases for non-f64 cases.

    Based on fuzz test from @craig.topper (detail/ViewSVN)
    by rksimon
  98. [X86][SSE] Add tests for underaligned nt stores

    Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) (detail/ViewSVN)
    by rksimon
  99. [llvm-nm] Additional lit tests for command line options

        Differential Revision: (detail/ViewSVN)
    by chrisj
  100. [X86][SSE] Add SSE4A nt store tests on X86 as well as X64

    We should be able to use MOVNTSD (f64) instead of MOVNTI (i32) to reduce the number of ops 32-bit targets

    Pulled out of D63246 (detail/ViewSVN)
    by rksimon
  101. [DebugInfo] Move Value struct out of DebugLocEntry as DbgValueLoc (NFC)

    Since the DebugLocEntry::Value is used as part of DwarfDebug and
    DebugLocEntry make it as the separate class.

    Reviewers: aprantl, dstenb

    Reviewed By: aprantl

    Differential Revision: (detail/ViewSVN)
    by nikolaprica
  102. [DebugInfo] Use FrameDestroy to extend stack locations to end-of-function

    We aim to ignore changes in variable locations during the prologue and
    epilogue of functions, to avoid using space documenting location changes
    that aren't visible. However in D61940 / r362951 this got ripped out as
    the previous implementation was unsound.

    Instead, use the FrameDestroy flag to identify when we're in the epilogue
    of a function, and ignore variable location changes accordingly. This fits
    in with existing code that examines the FrameSetup flag.

    Some variable locations get shuffled in modified tests as they now cover
    greater ranges, which is what would be expected. Some additional
    single-location variables are generated too. Two tests are un-xfailed,
    they were only xfailed due to r362951 deleting functionality they depended

    Apparently some out-of-tree backends don't accurately maintain FrameDestroy
    flags -- if you're an out-of-tree maintainer and see changes in variable
    locations disappear due to a faulty FrameDestroy flag, it's safe to back
    this change out. The impact is just slightly more debug info than necessary.

    Differential Revision: (detail/ViewSVN)
    by jmorse
  103. [ARM] Refactor handling of IT mask operands.

    During assembly, the mask operand to an IT instruction (storing the
    sequence of T/E for 'Then' and 'Else') is parsed out of the mnemonic
    into a representation that encodes 'Then' and 'Else' in the same way
    regardless of the condition code. At some point during encoding it has
    to be converted into the instruction encoding used in the
    architecture, in which the mask encodes a sequence of replacement
    low-order bits for the condition code, so that which bit value means
    'then' and which 'else' depends on whether the original condition code
    had its low bit set.

    Previously, that transformation was done by processInstruction(), half
    way through assembly. So an MCOperand storing an IT mask would
    sometimes store it in one format, and sometimes in the other,
    depending on where in the assembly pipeline you were. You can see this
    in diagnostics from `llvm-mc -debug -triple=thumbv8a -show-inst`, for
    example: if you give it an instruction such as `itete eq`, you'd see
    an `<MCOperand Imm:5>` in a diagnostic become `<MCOperand Imm:11>` in
    the final output.

    Having the same data structure store values with time-dependent
    semantics is confusing already, and it will get more confusing when we
    introduce the MVE VPT instruction which reuses the Then/Else bitmask
    idea in a different context. So I'm refactoring: now, all `ARMOperand`
    and `MCOperand` representations of an IT mask work exactly the same
    way, namely, 0 means 'Then' and 1 means 'Else', regardless of what
    original predicate is being referred to. The architectural encoding of
    IT that depends on the original condition is now constructed at the
    point when we turn the `MCOperand` into the final instruction bit
    pattern, and decoded similarly in the disassembler.

    The previous condition-independent parse-time format used 0 for Else
    and 1 for Then. I've taken the opportunity to flip the sense of it
    while I'm changing all of this anyway, because it seems to me more
    natural to use 0 for 'leave the starting condition unchanged' and 1
    for 'invert it', as if those bits were an XOR mask.

    Reviewers: ostannard

    Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by statham
  104. [llvm-objcopy] Implement IHEX reader

    This is the final part of IHEX format support in llvm-objcopy
    Differential revision: (detail/ViewSVN)
    by evgeny777
  105. [OpenCL] Move and remove unused include

    Patch by Pierre Gondois.

    Differential revision: (detail/ViewSVN)
    by svenvh
  106. [WebAssembly] Modernize include path handling

    Move include path construction from
    InitHeaderSearch::AddDefaultIncludePaths in the Driver which appears
    to be the more modern/correct way of doing things.

    Differential Revision: (detail/ViewSVN)
    by sbc
  107. Improve reduction intrinsics by overloading result value.

    This patch uses the mechanism from D62995 to strengthen the
    definitions of the reduction intrinsics by letting the scalar
    result/accumulator type be overloaded from the vector element type.

    For example:

      ; The LLVM LangRef specifies that the scalar result must equal the
      ; vector element type, but this is not checked/enforced by LLVM.
      declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a)

    This patch changes that into:

      declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a)

    Which has the type-constraint more explicit and causes LLVM to check
    the result type with the vector element type.

    Reviewers: RKSimon, arsenm, rnk, greened, aemerson

    Reviewed By: arsenm

    Differential Revision: (detail/ViewSVN)
    by s.desmalen
  108. Revert [llvm-ar][test] Add to MRI test coverage

    This reverts 363232 due to mru-utf8.test buildbot test failure

    Differential Revision: (detail/ViewSVN)
    by gbreynoo
  109. [clang-scan-deps] Fix -DBUILD_SHARED_LIBS=ON build

    The -DBUILD_SHARED_LIBS=ON build was broken in rL363204

    Differential Revision: (detail/ViewSVN)
    by sbc
  110. [clangd] Treat lambdas as functions when preparing hover response

    Reviewers: sammccall, ilya-biryukov

    Subscribers: MaskRay, jkorous, arphaman, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by kadircet
  111. [NFC] Simplify Call query

    Use getIntrinsicID() directly from IntrinsicInst. (detail/ViewSVN)
    by sam_parker
  112. [ARM][TTI] Scan for existing loop intrinsics

    TTI should report that it's not profitable to generate a hardware loop
    if it, or one of its child loops, has already been converted.

    Differential Revision: (detail/ViewSVN)
    by sam_parker
  113. [IntrinsicEmitter] Extend argument overloading with forward references.

    Extend the mechanism to overload intrinsic arguments by using either
    backward or forward references to the overloadable arguments.

    In for example:

      def int_something : Intrinsic<[LLVMPointerToElt<0>],
                                    [llvm_anyvector_ty], []>;

    LLVMPointerToElt<0> is a forward reference to the overloadable operand
    of type 'llvm_anyvector_ty' and would allow intrinsics such as:

      declare i32* @llvm.something.v4i32(<4 x i32>);
      declare i64* @llvm.something.v2i64(<2 x i64>);

    where the result pointer type is deduced from the element type of the
    first argument.

    If the returned pointer is not a pointer to the element type, LLVM will
    give an error:

      Intrinsic has incorrect return type!
      i64* (<4 x i32>)* @llvm.something.v4i32

    Reviewers: RKSimon, arsenm, rnk, greened

    Reviewed By: arsenm

    Differential Revision: (detail/ViewSVN)
    by s.desmalen
  114. [llvm-ar][test] Add to MRI test coverage

    This change adds tests to cover existing MRI script functionality.

    Differential Revision: (detail/ViewSVN)
    by gbreynoo
  115. [X86] Correct instruction operands in evex-to-vex-compress.mir to be closer to real instructions.

    $noreg was being used way more than it should have. We also had
    xmm registers in addressing modes.

    Mostly found by hacking the machine verifier to do some stricter
    checking that happened to work for this test, but not sure if
    generally applicable for other tests or other targets. (detail/ViewSVN)
    by ctopper
  116. clang-format extension: Widen the supported versions range

    So that it covers also the latest VS 2019 version.

    By Antonio Maiorano! (detail/ViewSVN)
    by hans

Started by upstream project clang-stage2-Rthinlto_relay build number 1613
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