Started 21 days ago
Took 12 hr on green-dragon-18

Failed Build #18254 (Jun 24, 2019 7:44:49 PM)

  • : 364247
  • : 364245
  • : 364231
  • : 363952
  • : 364241
  • : 364222
  1. [NFC] Add missing consts into memoryaccess_def_iterator (detail/ViewSVN)
    by Vitaly Buka
  2. [InstCombine] squash is-not-power-of-2 using ctpop

    This is the Demorgan'd 'not' of the pattern handled in:
    D63660 / rL364153

    This is another intermediate IR step towards solving PR42314:

    We can test if a value is not a power-of-2 using ctpop(X) > 1,
    so combining that with an is-zero check of the input is the
    same as testing if not exactly 1 bit is set:

    (X == 0) || (ctpop(X) u> 1) --> ctpop(X) != 1 (detail/ViewSVN)
    by spatel
  3. Fix test cl-response-file.c to work on all platforms including Windows/Solaris.

    Differential Revision: (detail/ViewSVN)
    by dyung
  4. AMDGPU/GlobalISel: Add tests for regbankselect of v2s16 and/or/xor (detail/ViewSVN)
    by arsenm
  5. Fix test failures due to modified wording in Clang diagnostics. (detail/ViewSVN)
    by rsmith
  6. Fix test failures when using a custom ABI namespace. (detail/ViewSVN)
    by rsmith
  7. [SLP] NFC: Fixed typo in comment (detail/ViewSVN)
    by vporpo
  8. [Syntax] Do not glue multiple empty PP expansions to a single mapping

    This change makes sure we have a single mapping for each macro expansion,
    even if the result of expansion was empty.

    To achieve that, we take information from PPCallbacks::MacroExpands into
    account. Previously we relied only on source locations of expanded tokens.

    Reviewers: sammccall

    Reviewed By: sammccall

    Subscribers: cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by ibiryukov
  9. InstCombine: Preserve nuw when reassociating nuw ops [3/3]

    Alive says this is OK. (detail/ViewSVN)
    by arsenm
  10. InstCombine: Preserve nuw when reassociating nuw ops [2/3]

    Alive says this is OK. (detail/ViewSVN)
    by arsenm
  11. InstCombine: Preserve nuw when reassociating nuw ops [1/3]

    Alive says this is OK. (detail/ViewSVN)
    by arsenm
  12. [NFC][Reassociate] Add unary FNeg tests to fast-ReassociateVector.ll (detail/ViewSVN)
    by mcinally
  13. (Reland with changes) Adding a function for setting coverage output file.

    User code can open a file on its own and pass it to the runtime, rather than
    specifying a name and having the runtime open the file. This supports the use
    case where a process cannot open a file on its own but can receive a file
    descriptor from another process.

    Relanding The original revision unlocked
    the file before calling flush, this revision fixes that.

    Reviewers: Dor1s, davidxl

    Reviewed By: Dor1s

    Subscribers: #sanitizers, llvm-commits

    Tags: #sanitizers, #llvm

    Differential Revision: (detail/ViewSVN)
    by sajjadm
  14. NFC: DataExtractor: use decodeULEB128 to implement getULEB128 (detail/ViewSVN)
    by dblaikie
  15. [CVP] Reenable nowrap flag inference

    Inference of nowrap flags in CVP has been disabled, because it
    triggered a bug in LFTR (
    This issue has been fixed in D60935, so we should be able to reenable
    nowrap flag inference now.

    Differential Revision: (detail/ViewSVN)
    by nikic
  16. [InstCombine] add tests for more variants of isPowerOf2; NFC (detail/ViewSVN)
    by spatel
  17. Augment location information when dumping the AST to JSON.

    Rather than create JSON objects for source locations and ranges, we instead stream them out directly. This allows us to elide duplicate information (without JSON field reordering causing an issue) like file names and line numbers, similar to the text dump. This also adds token length information when dumping the source location. (detail/ViewSVN)
    by aaronballman
  18. llvm-symbolizer: Add a FRAME command.

    This command prints a description of the referenced function's stack frame.
    For each formal parameter and local variable, the tool prints:

    - function name
    - variable name
    - file/line of declaration
    - FP-relative variable location (if available)
    - size in bytes
    - HWASAN tag offset

    This information will be used by the HWASAN runtime to identify local
    variables in UAR reports.

    Differential Revision: (detail/ViewSVN)
    by pcc
  19. [InstCombine] Regenerate test pr17827. NFCI.

    Prep work for upcoming patch D63505. (detail/ViewSVN)
    by huihuiz
  20. [clang-doc] Add basic support for templates and typedef

    In serialize::parseBases(...), when a base record is a template
    specialization, the specialization was used as the parent. It should be
    the base template so there is only one file generated for this record.
    When the specialized template is implicitly declared the reference USR
    corresponded to the GlobalNamespace's USR, this will now be the base
    template's USR.

    More information about templates will be added later.

    In serialize::emiInfo(RecorDecl*, ...), typedef records were not handled
    and the name was empty. This is now handled and a IsTypeDef attribute is
    added to RecordInfo struct.

    In serialize::emitInfo(CXXMethodDecl*, ...), template specialization is
    handled like in serialize::parseBases(...).

    Bitcode writer and reader are modified to handle the new attribute of

    Submitted on behalf of Diego Astiazarán (
    Differential Revision: (detail/ViewSVN)
    by juliehockett
  21. [CodeGen] Add missing vector type legalization for ctlz_zero_undef

    Widen vector result type for ctlz_zero_undef and cttz_zero_undef the same as
    ctlz and cttz.

    Differential Revision: (detail/ViewSVN)
    by froese
  22. [Tests] Add cases where we're failing to discharge provably loop exits (tests for D63733) (detail/ViewSVN)
    by reames
  23. [SLP] Support unary FNeg vectorization

    Differential Revision: (detail/ViewSVN)
    by mcinally
  24. Remove flag for no longer supported MSVC version (detail/ViewSVN)
    by nico
  25. AMDGPU/GlobalISel: Select G_TRUNC (detail/ViewSVN)
    by arsenm
  26. AMDGPU/GlobalISel: RegBankSelect for amdgcn.class (detail/ViewSVN)
    by arsenm
  27. [PowerPC][UpdateTestChecks] powerpc- triple support

    There are quite some old testcases with powerpc- triple,
    we should add this triple support so that we can update them with script.

    Differential Revision: (detail/ViewSVN)
    by jsji
  28. AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect

    Scalar extends to s64 can use S_BFE_{I64|U64}, but vector extends need
    to extend to the 32-bit half, and then to 64.

    I'm not sure what the line should be between what RegBankSelect
    handles, and what instruction select does, but for now I'm erring on
    the side of RegBankSelect for future post-RBS combines. (detail/ViewSVN)
    by arsenm
  29. [llvm-objdump] Match GNU objdump on symbol types shown in disassembly

    STT_OBJECT and STT_COMMON are dumped as data, not disassembled.

    Differential Revision: (detail/ViewSVN)
    by yuanfang
  30. [AMDGPU] Allow any value in unused src0 field in v_nop

    The LLVM disassembler assumes that the unused src0 operand of v_nop is
    zero. Other tools can put another value in that field, which is still
    valid. This commit fixes the LLVM disassembler to recognize such an
    encoding as v_nop, in the same way as we already do for s_getpc.

    Differential Revision:

    Change-Id: Iaf0363eae26ff92fc4ebc716216476adbff37a6f (detail/ViewSVN)
    by tpr
  31. [X86] Don't a vzext_movl in LowerBuildVectorv16i8/LowerBuildVectorv8i16 if there are no zeroes in the vector we're building.

    In LowerBuildVectorv16i8 we took care to use an any_extend if the first pair is in the lower 16-bits of the vector and no elements are 0. So bits [31:16] will be undefined. But we still emitted a vzext_movl to ensure that bits [127:32] are 0. If we don't need any zeroes we should be consistent and make all of 127:16 undefined.

    In LowerBuildVectorv8i16 we can just delete the vzext_movl code because we only use the scalar_to_vector when there are no zeroes. So the vzext_movl is always unnecessary.

    Found while investigating whether (vzext_movl (scalar_to_vector (loadi32)) patterns are necessary. At least one of the cases where they were necessary was where the loadi32 matched 32-bit aligned 16-bit extload. Seemed weird that we required vzext_movl for that case.

    Differential Revision: (detail/ViewSVN)
    by ctopper
  32. [X86] Cleanups and safety checks around the isFNEG

    This patch does a few things to start cleaning up the isFNEG function.

    -Remove the Op0/Op1 peekThroughBitcast calls that seem unnecessary. getTargetConstantBitsFromNode has its own peekThroughBitcast inside. And we have a separate peekThroughBitcast on the return value.
    -Add a check of the scalar size after the first peekThroughBitcast to ensure we haven't changed the element size and just did something like f32->i32 or f64->i64.
    -Remove an unnecessary check that Op1's type is floating point after the peekThroughBitcast. We're just going to look for a bit pattern from a constant. We don't care about its type.
    -Add VT checks on several places that consume the return value of isFNEG. Due to the peekThroughBitcasts inside, the type of the return value isn't guaranteed. So its not safe to use it to build other nodes without ensuring the type matches the type being used to build the node. We might be able to replace these checks with bitcasts instead, but I don't have a test case so a bail out check seemed better for now.

    Differential Revision: (detail/ViewSVN)
    by ctopper
  33. [AArch64] Regenerate vcvt tests. NFCI.

    Prep work for an upcoming patch (detail/ViewSVN)
    by rksimon
  34. [AArch64] Regenerate 2velem tests. NFCI.

    Prep work for an upcoming patch (detail/ViewSVN)
    by rksimon
  35. [AArch64] Regenerate merge-store tests. NFCI.

    Prep work for an upcoming patch (detail/ViewSVN)
    by rksimon
  36. [clang][NewPM] Add RUNS for tests that produce slightly different IR under new PM

    For CodeGenOpenCL/, the new PM produced a slightly different for
    loop, but this still checks for no loop unrolling as intended. This is
    committed separately from D63174. (detail/ViewSVN)
    by leonardchan
  37. [clang][NewPM] Remove exception handling before loading pgo sample profile data

    This patch ensures that SimplifyCFGPass comes before SampleProfileLoaderPass
    on PGO runs in the new PM and fixes clang/test/CodeGen/pgo-sample.c.

    Differential Revision: (detail/ViewSVN)
    by leonardchan
  38. [X86] Regenerate fast fadd reduction tests. NFCI

    Fix whitespace. (detail/ViewSVN)
    by rksimon
  39. AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1

    Try to fail for scc, since I don't think that should ever be produced. (detail/ViewSVN)
    by arsenm
  40. [bindings/go] Add debug information accessors

    Add debug information accessors, as provided in the following patches: (DILocation) metadata kind get/set debug location on a Value (DIScope)

    The API as proposed in this patch is similar to the current Value API,
    with a single root type and methods that are only valid for certain
    subclasses. I have considered just implementing generic Line() calls
    (that are valid on all DINodes that have a line) but the implementation
    of that got a bit awkward without support from the C API. I've also
    considered creating generic getters like a Metadata.DebugLoc() that
    returns a DebugLoc, but there is a mismatch between the Go DI nodes in
    the LLVM API and the actual DINode class hierarchy, so that's also hard
    to get right (without being confusing or breaking the API).

    Differential Revision: (detail/ViewSVN)
    by aykevl
  41. [analyzer] print() JSONify: ProgramPoint revision

    Summary: Now we also print out the filename with its path.

    Reviewers: NoQ

    Reviewed By: NoQ

    Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin,
                 mikhail.ramalho, Szelethus, donat.nagy, dkrupp, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by charusso
  42. Hexagon: Rename another copy of Register class

    For some reason clang is happy with the conflict, but MSVC is not. (detail/ViewSVN)
    by arsenm
  43. ARC: Fix -Wimplicit-fallthrough (detail/ViewSVN)
    by arsenm
  44. GlobalISel: Remove unsigned variant of SrcOp

    Force using Register.

    One downside is the generated register enums require explicit
    conversion. (detail/ViewSVN)
    by arsenm
  45. [analyzer] Fix JSON dumps for ExplodedNodes

    - Now we could see the `has_report` property in `trim-egraph` mode.
    - This patch also removes the trailing comma after each node.

    Reviewers: NoQ

    Reviewed By: NoQ

    Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin,
                 mikhail.ramalho, Szelethus, donat.nagy, dkrupp, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by charusso
  46. CodeGen: Introduce a class for registers

    Avoids using a plain unsigned for registers throughoug codegen.
    Doesn't attempt to change every register use, just something a little
    more than the set needed to build after changing the return type of
    MachineOperand::getReg(). (detail/ViewSVN)
    by arsenm
  47. [AMDGPU] Remove unused variable AllSGPRSpilledToVGPRs. NFC

    Removing the unused variable AllSGPRSpilledToVGPRs in
    to avoid
      error: variable 'AllSGPRSpilledToVGPRs' set but not used

    Reviewers: arsenm, nhaehnle

    Reviewed By: nhaehnle

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by bjope
  48. [OPENMP]Relax the test checks to pacify 32bit buildbots, NFC. (detail/ViewSVN)
    by abataev
  49. Hexagon: Rename Register class

    This avoids a naming conflict in a future patch. (detail/ViewSVN)
    by arsenm
  50. [InstCombine] reduce funnel-shift i16 X, X, 8 to bswap X

    Prefer the more exact intrinsic to remove a use of the input value
    and possibly make further transforms easier (we will still need
    to match patterns with funnel-shift of wider types as pieces of
    bswap, especially if we want to canonicalize to funnel-shift with
    constant shift amount). Discussed in D46760. (detail/ViewSVN)
    by spatel
  51. AMDGPU/GlobalISel: Fix RegBankSelect for s1 sext/zext/anyext

    This needs different handling if the source is known to be a valid
    condition or not. Handle turning it into shifts or a select during
    regbankselect. (detail/ViewSVN)
    by arsenm
  52. AMDGPU: Fold frame index into MUBUF

    This matters for byval uses outside of the entry block, which appear
    as copies.

    Previously, the only folding done was during selection, which could
    not see the underlying frame index. For any uses outside the entry
    block, the frame index was materialized in the entry block relative to
    the global scratch wave offset.

    This may produce worse code in cases where the offset ends up not
    fitting in the MUBUF offset field. A better heuristic would be helpfu
    for extreme frames. (detail/ViewSVN)
    by arsenm
  53. [InstCombine] add tests for funnel-shift to bswap; NFC (detail/ViewSVN)
    by spatel
  54. [CUDA][HIP] Don't set comdat attribute for CUDA device stub functions.\nDifferential Revision: (detail/ViewSVN)
    by kpyzhov
  55. AMDGPU: Cleanup checking when spills need emergency slots

    Address fixme, which should no longer be a problem since r363757. (detail/ViewSVN)
    by arsenm
  56. [InstCombine] SliceUpIllegalIntegerPHI - bail on out of range shifts

    trunc(lshr) handling - if the shift is out of range (undefined) then bail like we do for non-constant shifts.

    Fixes OSS Fuzz #15217 (detail/ViewSVN)
    by rksimon
  57. [clangd] Improve SelectionTree string representation (detail/ViewSVN)
    by sammccall
  58. [DAGCombine] visitMUL - allow shift by zero in MulByConstant.

    This can occur under certain circumstances when undefs are created later on in the constant multipliers (e.g. in this case due to SimplifyDemandedVectorElts). Its better to let the shift by zero to occur and perform any cleanup afterward.

    Fixes OSS Fuzz #15429 (detail/ViewSVN)
    by rksimon
  59. [ConstantFolding] Use hasVectorInstrinsicScalarOpd. NFC

    Use the hasVectorInstrinsicScalarOpd helper function
    in ConstantFoldVectorCall.

    Reviewers: rengolin, RKSimon, dblaikie

    Reviewed By: rengolin, RKSimon

    Subscribers: tschuett, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by bjope
  60. [Scalarizer] Add scalarizer support for smul.fix.sat

    Handle smul.fix.sat in the scalarizer. This is done by
    adding smul.fix.sat to the set of "isTriviallyVectorizable"

    The addition of smul.fix.sat in isTriviallyVectorizable and
    hasVectorInstrinsicScalarOpd can also be seen as a preparation
    to be able to use hasVectorInstrinsicScalarOpd in ConstantFolding.

    Reviewers: rengolin, RKSimon, dblaikie

    Reviewed By: rengolin

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by bjope

Started by upstream project clang-stage2-Rthinlto_relay build number 1662
originally caused by:

This run spent:

  • 53 min waiting;
  • 12 hr build duration;
  • 13 hr total from scheduled to completion.

Identified problems

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 1

Missing test results

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Indication 2

Ninja target failed

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Indication 3