FailedChanges

Summary

  1. [OPENMP]Fix use of local allocators in allocate clauses. (details)
  2. [OpenMP] change omp_atk_* and omp_atv_* enumerators to lowercase [NFC] (details)
  3. [X86][AVX] Add AVX1/AVX2 ashr vector tests (details)
  4. [SelectionDAG] ComputeNumSignBits - add ISD::SUB demanded elts support (details)
  5. [NFC][ARM] Add test (details)
  6. AMDGPU: Check for other uses when looking through casted select (details)
  7. [Alignment][NFC] Use Align with CreateAlignedStore (details)
  8. [X86][SSE] Add ComputeNumSignBits tests for (ADD (AND X, 1), -1) vectors (details)
  9. [SelectionDAG] ComputeNumSignBits - add ISD::ADD vector support (details)
  10. clang-cl: Parse /QIntel-jcc-erratum (details)
  11. GlobalISel: Use Register (details)
  12. AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32 (details)
  13. [RDA] Skip debug values (details)
  14. [analyzer] Improve FuchsiaHandleChecker's diagnostic messages (details)
  15. [Concepts] Placeholder constraints and abbreviated templates (details)
  16. [SelectionDAG] ComputeNumSignBits - add ISD::ADD demanded elts support (details)
  17. [X86] Add AVX512 tests for vector rotations (details)
  18. [X86] Add test showing failure to remove vector rotate by zero (details)
  19. [X86] LowerRotate - early out for vector rotates by zero (details)
  20. [mlir] Fix vectorize transform crashing on none-op operand (details)
  21. [SVE] Add SVE2 patterns for unpredicated multiply instructions (details)
Commit f3c508fe91606c7383c812838b07ed5433a00dcf by a.bataev
[OPENMP]Fix use of local allocators in allocate clauses.
If local allocator was declared and used in the allocate clause, it was
not captured in inner region. It leads to a compiler crash, need to
capture the allocator declarator.
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp (diff)
The file was modifiedclang/test/OpenMP/parallel_master_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/teams_distribute_ast_print.cpp (diff)
Commit ad24cf2a942068e5bcdda3fbe58c084715266cf3 by kkwli0
[OpenMP] change omp_atk_* and omp_atv_* enumerators to lowercase [NFC]
The OpenMP spec defines the OMP_ATK_* and OMP_ATV_* to be lowercase.
Differential Revision: https://reviews.llvm.org/D73248
The file was modifiedopenmp/runtime/test/api/omp_alloc_def_fb.c (diff)
The file was modifiedopenmp/runtime/test/api/omp_alloc_hbw.c (diff)
The file was modifiedopenmp/runtime/src/include/omp.h.var (diff)
The file was modifiedopenmp/runtime/src/kmp_alloc.cpp (diff)
The file was modifiedopenmp/runtime/test/api/omp_alloc_null_fb.c (diff)
The file was modifiedopenmp/runtime/src/kmp.h (diff)
Commit c1cac20827684949d381ae418f1868a76eaeda67 by llvm-dev
[X86][AVX] Add AVX1/AVX2 ashr vector tests
The file was modifiedllvm/test/CodeGen/X86/sar_fold64.ll (diff)
Commit fc5bbbf328bc2ef582cf1cf9ba5ac2ddfc12ea31 by llvm-dev
[SelectionDAG] ComputeNumSignBits - add ISD::SUB demanded elts support
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/sar_fold64.ll (diff)
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
Commit dfec702290e4cbd2fb965096788225ef3aac0986 by arsenm2
AMDGPU: Check for other uses when looking through casted select
Fixes mesa regression on ext_transform_feedback-max-varyings
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp (diff)
Commit 59f95222d4c5e997342b0514984823a99a16d44b by gchatelet
[Alignment][NFC] Use Align with CreateAlignedStore
Summary: This is patch is part of a series to introduce an Alignment
type. See this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this
patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet, bollu
Subscribers: arsenm, jvesely, nhaehnle, hiraditya, kerbowa, cfe-commits,
llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D73274
The file was modifiedclang/lib/CodeGen/CGBuilder.h (diff)
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp (diff)
The file was modifiedllvm/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp (diff)
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp (diff)
The file was modifiedllvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp (diff)
The file was modifiedllvm/include/llvm/IR/GlobalObject.h (diff)
The file was modifiedllvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (diff)
The file was modifiedllvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp (diff)
The file was modifiedllvm/include/llvm/IR/IRBuilder.h (diff)
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (diff)
The file was modifiedllvm/lib/Target/X86/X86InterleavedAccess.cpp (diff)
The file was modifiedllvm/include/llvm/IR/DataLayout.h (diff)
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp (diff)
The file was modifiedpolly/lib/CodeGen/RuntimeDebugBuilder.cpp (diff)
The file was modifiedllvm/lib/Transforms/Scalar/Scalarizer.cpp (diff)
The file was modifiedclang/lib/CodeGen/CGGPUBuiltin.cpp (diff)
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp (diff)
The file was modifiedllvm/lib/IR/DataLayout.cpp (diff)
The file was modifiedpolly/lib/CodeGen/BlockGenerators.cpp (diff)
The file was modifiedllvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp (diff)
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp (diff)
The file was modifiedclang/lib/CodeGen/CGBlocks.cpp (diff)
The file was modifiedllvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp (diff)
The file was modifiedllvm/lib/Transforms/IPO/LowerTypeTests.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp (diff)
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp (diff)
The file was modifiedpolly/lib/CodeGen/LoopGeneratorsKMP.cpp (diff)
The file was modifiedclang/lib/CodeGen/CGObjCGNU.cpp (diff)
Commit d1de6dc17cdd37f84e92da5a456099eab0cc1467 by llvm-dev
[X86][SSE] Add ComputeNumSignBits tests for (ADD (AND X, 1), -1) vectors
The file was modifiedllvm/test/CodeGen/X86/sar_fold64.ll (diff)
Commit 0fec8acdd82a69fc5419b4a9db3c92a86634729d by llvm-dev
[SelectionDAG] ComputeNumSignBits - add ISD::ADD vector support
Add missing handling for (ADD (AND X, 1), -1) uniform vectors
The file was modifiedllvm/test/CodeGen/X86/sar_fold64.ll (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (diff)
Commit e256a775ebfcda5fd5f4d05fe40f6bb029e88f29 by hans
clang-cl: Parse /QIntel-jcc-erratum
It appears to be a new flag, see
https://github.com/MicrosoftDocs/cpp-docs/commit/c7ac1c2635a631c61d3bed9f12b31dee6d6716fe
The file was modifiedclang/include/clang/Driver/CLCompatOptions.td (diff)
The file was modifiedclang/test/Driver/cl-options.c (diff)
Commit 4faf71a14338420afc09eec261d5295439ae956a by arsenm2
GlobalISel: Use Register
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h (diff)
Commit 618fa77ae4dd8244e468fce0bf144fa329f41e5b by arsenm2
AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32
The other 3-op patterns should also be theoretically handled, but
currently there's a bug in the inferred pattern complexity.
I'm not sure what the error handling strategy should be for potential
constant bus violations. I think the correct strategy is to never
produce mixed SGPR and VGPR operands in a typical VOP instruction, which
will trivially avoid them. However, it's possible to still have hand
written MIR (or erroneously transformed code) with these operands. When
these fold, the restriction will be violated. We currently don't have
any verifiers for reg bank legality. For now, just ignore the
restriction.
It might be worth triggering a DAG fallback on verifier error.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll (diff)
Commit 05532575e88a45774dcf470d4639a01a4e501f66 by sam.parker
[RDA] Skip debug values
Skip debug instructions when iterating through a block to find uses.
Differential Revision: https://reviews.llvm.org/D73273
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp (diff)
Commit 5911268e441cc78f7c81f931dd64ed2c63078e8e by xazax
[analyzer] Improve FuchsiaHandleChecker's diagnostic messages
Differential Revision: https://reviews.llvm.org/D73229
The file was modifiedclang/test/Analysis/fuchsia_handle.cpp (diff)
The file was modifiedclang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp (diff)
Commit b481f028144ca91c15d1db3649ce14f174259e7e by saar
[Concepts] Placeholder constraints and abbreviated templates
This patch implements P1141R2 "Yet another approach for constrained
declarations".
General strategy for this patch was:
- Expand AutoType to include optional type-constraint, reflecting the
wording and easing the integration of constraints.
- Replace autos in parameter type specifiers with invented parameters in
GetTypeSpecTypeForDeclarator, using the same logic
previously used for generic lambdas, now unified with abbreviated
templates, by:
- Tracking the template parameter lists in the Declarator object
- Tracking the template parameter depth before parsing function
declarators (at which point we can match template
   parameters against scope specifiers to know if we have an explicit
template parameter list to append invented parameters
   to or not).
- When encountering an AutoType in a parameter context we check a stack
of InventedTemplateParameterInfo structures that
contain the info required to create and accumulate invented template
parameters (fields that were already present in
LambdaScopeInfo, which now inherits from this class and is looked up
when an auto is encountered in a lambda context).
Resubmit after fixing MSAN failures caused by incomplete initialization
of AutoTypeLocs in TypeSpecLocFiller.
Differential Revision: https://reviews.llvm.org/D65042
The file was modifiedclang/lib/Serialization/ASTReader.cpp (diff)
The file was modifiedclang/include/clang/Sema/Scope.h (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
The file was modifiedclang/lib/AST/TypePrinter.cpp (diff)
The file was modifiedclang/include/clang/AST/TypeProperties.td (diff)
The file was modifiedclang/lib/AST/DeclTemplate.cpp (diff)
The file was modifiedclang/lib/AST/ASTStructuralEquivalence.cpp (diff)
The file was modifiedclang/include/clang/AST/RecursiveASTVisitor.h (diff)
The file was modifiedclang/include/clang/Sema/DeclSpec.h (diff)
The file was modifiedclang/include/clang/Sema/ScopeInfo.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticParseKinds.td (diff)
The file was modifiedclang/lib/AST/ASTImporter.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td (diff)
The file was modifiedclang/lib/AST/ASTContext.cpp (diff)
The file was modifiedclang/test/AST/ast-dump-record-definition-data-json.cpp (diff)
The file was modifiedclang/lib/Sema/SemaDecl.cpp (diff)
The file was addedclang/test/CXX/dcl/dcl.spec/dcl.type/dcl.spec.auto/p6.cpp
The file was modifiedclang/include/clang/AST/PropertiesBase.td (diff)
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp (diff)
The file was modifiedclang/test/CXX/temp/temp.param/p10-2a.cpp (diff)
The file was modifiedclang/lib/Parse/ParseTentative.cpp (diff)
The file was modifiedclang/test/SemaCXX/cxx1y-generic-lambdas.cpp (diff)
The file was modifiedclang/include/clang/AST/DeclTemplate.h (diff)
The file was modifiedclang/test/CXX/expr/expr.prim/expr.prim.lambda/expr.prim.lambda.closure/p3.cpp (diff)
The file was modifiedclang/lib/AST/TextNodeDumper.cpp (diff)
The file was addedclang/test/Parser/cxx2a-placeholder-type-constraint.cpp
The file was modifiedclang/lib/Parse/ParseCXXInlineMethods.cpp (diff)
The file was modifiedclang/lib/Sema/Sema.cpp (diff)
The file was modifiedclang/lib/Sema/SemaLambda.cpp (diff)
The file was modifiedclang/lib/Serialization/ASTWriterDecl.cpp (diff)
The file was modifiedclang/test/SemaTemplate/ms-delayed-default-template-args.cpp (diff)
The file was modifiedclang/include/clang/AST/Type.h (diff)
The file was modifiedclang/include/clang/AST/ASTContext.h (diff)
The file was modifiedclang/include/clang/AST/TemplateBase.h (diff)
The file was modifiedclang/lib/Parse/ParseDecl.cpp (diff)
The file was modifiedclang/lib/Parse/Parser.cpp (diff)
The file was modifiedclang/lib/AST/TemplateBase.cpp (diff)
The file was modifiedclang/lib/Sema/SemaType.cpp (diff)
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp (diff)
The file was modifiedclang/lib/Sema/DeclSpec.cpp (diff)
The file was modifiedclang/lib/Sema/TreeTransform.h (diff)
The file was modifiedclang/lib/AST/TypeLoc.cpp (diff)
The file was modifiedclang/lib/AST/Type.cpp (diff)
The file was modifiedclang/lib/Parse/ParseTemplate.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp (diff)
The file was modifiedclang/lib/Parse/ParseDeclCXX.cpp (diff)
The file was modifiedclang/lib/AST/ODRHash.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplate.cpp (diff)
The file was modifiedclang/include/clang/AST/TypeLoc.h (diff)
The file was addedclang/test/CXX/dcl/dcl.fct/p17.cpp
The file was modifiedclang/lib/Serialization/ASTWriter.cpp (diff)
The file was modifiedclang/lib/Serialization/ASTReaderDecl.cpp (diff)
The file was modifiedclang/include/clang/AST/ASTNodeTraverser.h (diff)
Commit e25eee4db78f6374005fc7e1fd1a5e14a8c393ce by llvm-dev
[SelectionDAG] ComputeNumSignBits - add ISD::ADD demanded elts support
The file was modifiedllvm/test/CodeGen/X86/sar_fold64.ll (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (diff)
Commit 98e37af27231a8927bb8d8cbff9cd54a7aa165c6 by llvm-dev
[X86] Add AVX512 tests for vector rotations
The file was modifiedllvm/test/CodeGen/X86/rotate_vec.ll (diff)
Commit e4a58bd53860686701866580e43caefe70f45fd7 by llvm-dev
[X86] Add test showing failure to remove vector rotate by zero
The file was modifiedllvm/test/CodeGen/X86/rotate_vec.ll (diff)
Commit 0ec25a0316165899d2f02495b25cd6edcd8ef44b by llvm-dev
[X86] LowerRotate - early out for vector rotates by zero
The file was modifiedllvm/test/CodeGen/X86/rotate_vec.ll (diff)
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp (diff)
Commit 8d1ed2940d95d296ed24021e201dfcd31c2ea51d by ataei
[mlir] Fix vectorize transform crashing on none-op operand
The file was modifiedmlir/lib/Transforms/Vectorize.cpp (diff)
Commit 58ceb81d318b9a39f651e18ed68f8083e21719a0 by danilo.carvalho.grael
[SVE] Add SVE2 patterns for unpredicated multiply instructions
Summary: Add patterns for SVE2 unpredicated multiply instructions:
- mul, smulh, umulh, pmul, sqdmulh, sqrdmulh
Reviewers: sdesmalen, huntergr, efriedma, c-rhodes, kmclaughlin,
rengolin
Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits, amehsan
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72799
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td (diff)
The file was modifiedllvm/test/CodeGen/AArch64/sve-int-mul-pred.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (diff)
The file was modifiedllvm/test/CodeGen/AArch64/sve-int-arith-imm.ll (diff)
The file was addedllvm/test/CodeGen/AArch64/sve2-int-mul.ll
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td (diff)
The file was removedllvm/test/CodeGen/AArch64/sve-neg-int-arith-imm-2.ll
The file was removedllvm/test/CodeGen/AArch64/sve-neg-int-arith-imm.ll