Changes

[OPENMP]Fix use of local allocators in allocate clauses.
If local allocator was declared and used in the allocate clause, it was 
not captured in inner region. It leads to a compiler crash, need to 
capture the allocator declarator.

[OpenMP] change omp_atk_* and omp_atv_* enumerators to lowercase [NFC]
The OpenMP spec defines the OMP_ATK_* and OMP_ATV_* to be lowercase.
Differential Revision: https://reviews.llvm.org/D73248

[X86][AVX] Add AVX1/AVX2 ashr vector tests

[SelectionDAG] ComputeNumSignBits - add ISD::SUB demanded elts support

[NFC][ARM] Add test

AMDGPU: Check for other uses when looking through casted select
Fixes mesa regression on ext_transform_feedback-max-varyings

[Alignment][NFC] Use Align with CreateAlignedStore
Summary: This is patch is part of a series to introduce an Alignment
type. See this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this
patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet, bollu
Subscribers: arsenm, jvesely, nhaehnle, hiraditya, kerbowa, cfe-commits,
llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D73274

[X86][SSE] Add ComputeNumSignBits tests for (ADD (AND X, 1), -1) vectors

[SelectionDAG] ComputeNumSignBits - add ISD::ADD vector support
Add missing handling for (ADD (AND X, 1), -1) uniform vectors

clang-cl: Parse /QIntel-jcc-erratum
It appears to be a new flag, see 
https://github.com/MicrosoftDocs/cpp-docs/commit/c7ac1c2635a631c61d3bed9f12b31dee6d6716fe

GlobalISel: Use Register

AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32
The other 3-op patterns should also be theoretically handled, but 
currently there's a bug in the inferred pattern complexity.
I'm not sure what the error handling strategy should be for potential 
constant bus violations. I think the correct strategy is to never 
produce mixed SGPR and VGPR operands in a typical VOP instruction, which
will trivially avoid them. However, it's possible to still have hand
written MIR (or erroneously transformed code) with these operands. When
these fold, the restriction will be violated. We currently don't have
any verifiers for reg bank legality. For now, just ignore the
restriction.
It might be worth triggering a DAG fallback on verifier error.

[RDA] Skip debug values
Skip debug instructions when iterating through a block to find uses.
Differential Revision: https://reviews.llvm.org/D73273

[analyzer] Improve FuchsiaHandleChecker's diagnostic messages
Differential Revision: https://reviews.llvm.org/D73229

[Concepts] Placeholder constraints and abbreviated templates
This patch implements P1141R2 "Yet another approach for constrained
declarations".
General strategy for this patch was:
- Expand AutoType to include optional type-constraint, reflecting the
wording and easing the integration of constraints.
- Replace autos in parameter type specifiers with invented parameters in
GetTypeSpecTypeForDeclarator, using the same logic
 previously used for generic lambdas, now unified with abbreviated
templates, by:
 - Tracking the template parameter lists in the Declarator object
 - Tracking the template parameter depth before parsing function
declarators (at which point we can match template
   parameters against scope specifiers to know if we have an explicit
template parameter list to append invented parameters
   to or not).
- When encountering an AutoType in a parameter context we check a stack
of InventedTemplateParameterInfo structures that
 contain the info required to create and accumulate invented template
parameters (fields that were already present in
 LambdaScopeInfo, which now inherits from this class and is looked up
when an auto is encountered in a lambda context).
Resubmit after fixing MSAN failures caused by incomplete initialization
of AutoTypeLocs in TypeSpecLocFiller.
Differential Revision: https://reviews.llvm.org/D65042

[SelectionDAG] ComputeNumSignBits - add ISD::ADD demanded elts support

[X86] Add AVX512 tests for vector rotations

[X86] Add test showing failure to remove vector rotate by zero

[X86] LowerRotate - early out for vector rotates by zero

[mlir] Fix vectorize transform crashing on none-op operand

[SVE] Add SVE2 patterns for unpredicated multiply instructions
Summary: Add patterns for SVE2 unpredicated multiply instructions:
- mul, smulh, umulh, pmul, sqdmulh, sqrdmulh
Reviewers: sdesmalen, huntergr, efriedma, c-rhodes, kmclaughlin,
rengolin
Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits, amehsan
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72799