SuccessChanges

Summary

  1. [AMDGPU] Make SGPR spills exec mask agnostic (details)
  2. Fix build: TableGen uses `is<T>` instead of `isa<T>` as predicate (details)
  3. [lldb/Interpreter] Remove redundant argument (NFC) (details)
Commit da33c96d4762e0e59f1eff16f60d5c1575490331 by carl.ritson
[AMDGPU] Make SGPR spills exec mask agnostic

Explicitly set the exec mask for SGPR spills and reloads.
This fixes a bug where SGPR spills to memory could be incorrect
if the exec mask was 0 (or differed between spill and reload).

Additionally pack scalar subregisters (upto 16/32 per VGPR),
so that the majority of scalar types can be spilt or reloaded
with a simple memory access.  This should amortize some of the
additional overhead of manipulating the exec mask.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D80282
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-m0.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll (diff)
The file was addedllvm/test/CodeGen/AMDGPU/sgpr-spill.mir
Commit 48c800cc1bff13d1f5ae5e457a064cf6627280f1 by joker.eph
Fix build: TableGen uses `is<T>` instead of `isa<T>` as predicate
The file was modifiedmlir/lib/TableGen/Operator.cpp (diff)
Commit def72b91950d44a68b8613f25fa1a09926171222 by Jonas Devlieghere
[lldb/Interpreter] Remove redundant argument (NFC)
The file was modifiedlldb/source/Interpreter/CommandReturnObject.cpp (diff)