Started 3 mo 15 days ago
Took 10 hr on green-dragon-15

Failed Build #6423 (Jun 9, 2019 2:46:14 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 362913
  • http://llvm.org/svn/llvm-project/cfe/trunk : 362887
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 362859
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 362745
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 362866
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 362811
Changes
  1. Revert r361953 "[SVE][IR] Scalable Vector IR Type"

    This reverts commit f4fc01f8dd3a5dfd2060d1ad0df6b90e8351ddf7.
    It caused a 3-4x slowdown when doing thinlto links, PR42210. (detail)
    by nico
  2. [TargetLowering] Simplify (ctpop x) == 1

    Reviewers: craig.topper, spatel, RKSimon, bkramer

    Reviewed By: spatel

    Subscribers: javed.absar, lebedev.ri, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D63004 (detail)
    by xbolva00
  3. [InstCombine] foldICmpWithLowBitMaskedVal(): 'icmp sgt/sle': avoid miscompiles

    A precondition 'x != 0' was forgotten by me:
    https://rise4fun.com/Alive/JFNP
    https://rise4fun.com/Alive/jHvL

    These 4 folds with non-constants could be re-enabled,
    but for now let's go for the simplest solution.

    https://bugs.llvm.org/show_bug.cgi?id=42198 (detail)
    by lebedevri
  4. [NFC][InstCombine] Revisit canonicalize-constant-low-bit-mask-and-icmp-s* tests in preparatio for PR42198.

    The `icmp sgt`/`icmp sle` variants are, too, miscompiles:
    https://rise4fun.com/Alive/JFNP
    https://rise4fun.com/Alive/jHvL
    A precondition 'x != 0' was forgotten by me.

    While ensuring test coverage for `-1`, also add test coverage
    for `0` mask. Mask `0` is allowed for all the folds,
    mask `-1` is allowed for all the folds with unsigned `icmp` pred.
    Constant mask `0` is missed though.

    https://bugs.llvm.org/show_bug.cgi?id=42198 (detail)
    by lebedevri
  5. [InstCombine] change canonicalization to fabs() to use FMF on fneg

    This isn't the ideal fix (use FMF on the select), but it's still an
    improvement until we have better FMF propagation to selects and other
    FP math operators.

    I don't think there's much risk of regression from this change by
    not including the FMF on the fcmp any more. The nsz/nnan FMF
    should be the same on the fcmp and the fneg (fsub) because they
    have the same operand.

    This works around the most glaring FMF logical inconsistency cited
    in PR38086:
    https://bugs.llvm.org/show_bug.cgi?id=38086 (detail)
    by spatel
  6. [NFC] Adjust test for D63004 (detail)
    by xbolva00
  7. [NFC] Added test from PR19758 (detail)
    by xbolva00
  8. [NFC] Added test from PR42084 for D63058 (detail)
    by xbolva00
  9. [InstCombine] Add tests for usub.sat(x,y)+y etc; NFC

    For PR42178. (detail)
    by nikic
  10. [InstSimplify] reduce code duplication for fcmp folds; NFC (detail)
    by spatel
  11. [InstSimplify] enhance fcmp fold with never-nan operand

    This is another step towards correcting our usage of fast-math-flags when applied on an fcmp.
    In this case, we are checking for 'nnan' on the fcmp itself rather than the operand of
    the fcmp. But I'm leaving that clause in until we're more confident that we can stop
    relying on fcmp's FMF.

    By using the more general "isKnownNeverNaN()", we gain a simplification shown on the
    tests with 'uitofp' regardless of the FMF on the fcmp (uitofp never produces a NaN).
    On the tests with 'fabs', we are now relying on the FMF for the call fabs instruction
    in addition to the FMF on the fcmp.

    This is a continuation of D62979 / rL362879. (detail)
    by spatel
  12. [InstSimplify] add tests for fcmp with known-never-nan operands; NFC

    Opposite predicate for rL362742 / rL362879 / D62979 (detail)
    by spatel
  13. [MIR] Add simple PRE pass to MachineCSE

    This is the second part of the commit fixing PR38917 (hoisting
    partitially redundant machine instruction). Most of PRE (partitial
    redundancy elimination) and CSE work is done on LLVM IR, but some of
    redundancy arises during DAG legalization. Machine CSE is not enough
    to deal with it. This simple PRE implementation works a little bit
    intricately: it passes before CSE, looking for partitial redundancy
    and transforming it to fully redundancy, anticipating that the next
    CSE step will eliminate this created redundancy. If CSE doesn't
    eliminate this, than created instruction will remain dead and eliminated
    later by Remove Dead Machine Instructions pass.

    The third part of the commit is supposed to refactor MachineCSE,
    to make it more clear and to merge MachinePRE with MachineCSE,
    so one need no rely on further Remove Dead pass to clear instrs
    not eliminated by CSE.

    First step: https://reviews.llvm.org/D54839

    Fixes llvm.org/PR38917

    This is fixed recommit of r361356 after PowerPC64 multistage build failure. (detail)
    by anton-afanasyev

Started by upstream project clang-stage2-cmake-RgSan_relay build number 1138
originally caused by:

This run spent:

  • 2 ms waiting;
  • 10 hr build duration;
  • 10 hr total from scheduled to completion.
Test Result (no failures)

    Identified problems

    Ninja target failed

    Below is a link to the first failed ninja target.
    Indication 1

    Regression test failed

    This build failed because a regression test in the test suite FAILed. See the test report for details.
    Indication 2