Started 1 mo 8 days ago
Took 10 hr on green-dragon-06

Success Build #7362 (Sep 17, 2020 9:11:09 PM)


Git (git http://labmaster3.local/git/llvm-zorg.git)

  1. Changed to use cmake arguments to specify C and C++ compilers. (detail)

Git (git http://labmaster3.local/git/llvm-project.git)

  1. [compiler-rt] [scudo] Fix typo in function attribute (detail)
  2. [ARM] Sink splats to MVE intrinsics (detail)
  3. [amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel. (detail)
  4. [libc++] Remove some workarounds for missing variadic templates (detail)
  5. [Coroutine] Fix a bug where Coroutine incorrectly spills phi and invoke defs before CoroBegin (detail)
  6. [OpenMP 5.0] Fix user-defined mapper privatization in tasks (detail)
  7. [DFSan] Add bcmp wrapper. (detail)
  8. Precommit test updates (detail)
  9. [AArch64] Match pairwise add/fadd pattern (detail)
  10. [CUDA][HIP] Defer overloading resolution diagnostics for host device functions (detail)
  11. [ARM] Add more MVE postinc distribution tests. NFC (detail)
  12. [mlir][openacc] Change operand type from index to AnyInteger in parallel op (detail)
  13. [flang][openacc] Lower clauses on loop construct to OpenACC dialect (detail)
  14. [Test] Add tests showing that IndVars cannot prove (X + 1 > X) (detail)
  15. Revert "[DFSan] Add bcmp wrapper." (detail)
  16. ModuloSchedule.cpp - remove unnecessary includes. NFCI. (detail)
  17. Fix build failure in clangd (detail)
  18. [mlir][Vector] Add a folder for vector.broadcast (detail)
  19. [AArch64][GlobalISel] Fix bug in fewVectorElts action while legalizing oversize G_FPTRUNC vectors. (detail)
  20. [ARM] Expand distributing increments to also handle existing pre/post inc instructions. (detail)
  21. [InstSimplify] add tests for FP constant miscompile; NFC (PR43907) (detail)
  22. [amdgpu] Compilation fix for Release (detail)
  23. [SyntaxTree][Synthesis] Fix allocation in `createTree` for more general use (detail)
  24. [DFSan] Add bcmp wrapper. (detail)
  25. [Sema] Introduce BuiltinAttr, per-declaration builtin-ness (detail)
  26. [AMDGPU] Fix ROCm unit test memref initialization (detail)
  27. Add missing include (detail)
  28. [PowerPC][AIX] Don't hardcode python invoke command line (detail)
  29. [VectorCombine] add test for multi-use load (PR47558); NFC (detail)
  30. [VectorCombine] rearrange bailouts for load insert for efficiency; NFC (detail)
  31. Revert "[CUDA][HIP] Defer overloading resolution diagnostics for host device functions" (detail)
  32. Revert "[NFC] Refactor DiagnosticBuilder and PartialDiagnostic" (detail)
  33. [MLIR] Support for return values in Affine.For yield (detail)
  34. [MLIR][Affine] Add parametric tile size support for affine.for tiling (detail)
  35. [X86] Don't match x87 register inline asm constraints unless the VT is floating point or its a clobber (detail)
  36. [VectorCombine] limit load+insert transform to one-use (detail)
  37. [AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal for shifts. (detail)
  38. [AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b. (detail)
  39. [PDB] Split TypeServerSource and extend type index map lifetime (detail)
  40. [SVE][WIP] Implement lowering for fixed length VSELECT to Scalable (detail)
  41. [IRSim] Adding IR Instruction Mapper (detail)
  42. [gn build] Port 7e4c6fb8546 (detail)
  43. AArch64::ArchKind's underlying type is uint64_t (detail)
  44. [Lsan] Use fp registers to search for pointers (detail)
  45. Disable hoisting MI to hotter basic blocks when using pgo (detail)
  46. [SCEV] Add test cases for max BTC with loop guard info. (detail)
  47. [GVN] Add additional assume tests (NFC) (detail)
  48. [GVN] Use that assume(!X) implies X==false (PR47496) (detail)
  49. [LoopUnrollAndJam] Allow unroll and jam loops forced by user. (detail)
  50. [InstCombine] Canonicalize SPF_ABS to abs intrinc (detail)
  51. [llvm-install-name-tool] Update the command-line guide (detail)
  52. [NewPM] Fix pr45927.ll under NPM (detail)
  53. [MemorySSA] Be more conservative when traversing MemoryPhis. (detail)
  54. Support dwarf fission for wasm object files (detail)
  55. [TargetRegisterInfo] Add a couple of target hooks for the greedy register allocator (detail)
  56. [test] Fix FullUnroll.ll (detail)
  57. [AArch64] Enable implicit null check transformation (detail)
  58. [RISCV] Support Shadow Call Stack (detail)
  59. [MLIR][TableGen] Automatic detection and elimination of redundant methods (detail)
  60. [MemorySSA] Fix an unused variable warning [NFC] (detail)
  61. [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang (detail)
  62. [PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests (detail)
  63. [AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC. (detail)
  64. [AArch64][GlobalISel] Make G_STORE <8 x s8> legal. (detail)
  65. [lldb] Clarify docstring for SBBlock::IsInlined, NFC (detail)
  66. [mlir][shape] Add `shape.cstr_require %bool` (detail)
  67. [MLIR] Fix build failure due to (detail)
  68. [scudo/standalone] Don't define test main function for Fuchsia (detail)
  69. [NFC][Lsan] Fix zero-sized array compilation error (detail)
  70. [NFC] clang-format one line (detail)

Started by upstream project clang-stage2-cmake-RgSan_relay build number 3026
originally caused by:

This run spent:

  • 1 hr 8 min waiting;
  • 10 hr build duration;
  • 11 hr total from scheduled to completion.
Revision: 55edf7039e22312790ac950305746262d2856d97
  • detached
Revision: 94e652786cb7bbf750d37816c4f099aa4081f4be
  • refs/remotes/origin/master
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 7,348.
  • Still 379 days before reaching the previous zero warnings highscore.
Test Result (no failures)