Changes

[X86] Don't disassemble wbinvd with 0xf2 or 0x66 prefix.

The 0xf3 prefix has been defined as wbnoinvd on Icelake Server. So
the prefix isn't ignored by the CPU. AMD documentation suggests that
wbnoinvd is treated as wbinvd on older processors. Intel documentation
is not clear. Perhaps 0xf2 and 0x66 are treated the same, but its
not documented.

This patch changes TB to PS in the td file so 0xf2 and 0x66 will
be treated as errors. This matches versions of objdump after
wbnoinvd was added.

[AMDGPU] Avoid offset register in MUBUF for direct stack object accesses

We use an absolute address for stack objects and
it would be necessary to have a constant 0 for soffset field.

Fixes: SWDEV-228562

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D89234

[clangd] Add dependency on remote index service proto

It requires Index.proto to be built first. Failed builds:
https://github.com/clangd/clangd/runs/1305985916

[IndVars] Use contextual knowledge when proving trivial conds

No exact example where it would help, but it's a generally a more
powerful way to prove predicates.

[NFC] Factor out common code into lambda for further improvement

[NFC] Remove unused funciton param

Fix broken build after previous commit

[VE] Support atomic fence

Support atomic fence instruction and add a regression test.
Add MEMBARRIER pseudo insturction also to use it as a barrier
against to the compiler optimizations.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90112

[Schedule] Add a MultiHazardRecognizer

This adds a MultiHazardRecognizer and starts to make use of it in the
ARM backend. The idea of the class is to allow multiple independent
hazard recognizers to be added to a single base MultiHazardRecognizer,
allowing them to all work in parallel without requiring them to be
chained into subclasses. They can then be added or not based on cpu or
subtarget features, which will become useful in the ARM backend once
more hazard recognizers are being used for various things.

This also renames ARMHazardRecognizer to ARMHazardRecognizerFPMLx in the
process, to more clearly explain what that recognizer is designed for.

Differential Revision: https://reviews.llvm.org/D72939

[gn build] Port 61bc18de0b2

[ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90045

[ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90029

[ARM][SchedModels] Get rid of IsLdrAm2ScaledPred

Differential revision: https://reviews.llvm.org/D90024

[VE] Support atomic load

Support atomic load instruction and add a regression test.
VE uses release consitency, so need to insert fence around
atomic instructions.  This patch enable AtomicExpandPass
and use emitLeadingFence and emitTrailingFence mechanism
for such purpose.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90135

[PowerPC] Add test case for pr47830. NFC.

[ARM][SchedModels] Rename and generalize predicate. NFC

[AMDGPU] Emit new pal metadata by default

If no pal metadata is given, default to the msgpack format instead of
the legacy metadata. This makes tests better readable.

Differential Revision: https://reviews.llvm.org/D90035

[AsmPrinter] Add per BB instruction mix remark.

This patch adds a remarks that provides counts for each opcode per basic block.

An snippet of the generated information can be seen below.

The current implementation uses the target specific opcode for the counts. For example, on AArch64 this means we currently get 2 entries for `add` instructions if the block contains 32 and 64 bit adds. Similarly, immediate version are treated differently.

Unfortunately there seems to be no convenient way to get only the mnemonic part of the instruction as a string AFAIK. This could be improved in the future.

```
--- !Analysis
Pass:            asm-printer
Name:            InstructionMix
DebugLoc:        { File: arm64-instruction-mix-remarks.ll, Line: 30, Column: 30 }
Function:        foo
Args:
  - String:          'BasicBlock: '
  - BasicBlock:      else
  - String:          "\n"
  - String:          INST_MADDWrrr
  - String:          ': '
  - INST_MADDWrrr:   '2'
  - String:          "\n"
  - String:          INST_MOVZWi
  - String:          ': '
  - INST_MOVZWi:     '1'
```

Reviewed By: anemet, thegameg, paquette

Differential Revision: https://reviews.llvm.org/D89892

[VE] Add integer arithmetic vector instructions

Add VADD/VADS/VADX/VSUB/VSBS/VSBX/VMPY/VMPS/VMPX/VMPD/VDIV/VDVS/VDVX
instructions.  Also add regression tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89642

[VE] Add vector comparison and min/max

Add VCMP/VCPS/VCPX/VCMS/VCMX vector instructions.  Also add regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89643

[Annotation] Allows annotation to carry some additional constant arguments.

This allows using annotation in a much more contexts than it currently has.
especially when annotation with template or constexpr.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D88645

[flang] Tighten rules to resolve procedure as intrinsic procedure

2 Bug fixes:

- Do not resolve procedure as intrinsic if they appeared in an
  EXTERNAL attribute statement (one path was not considering this flag)

- Emit an error if a procedure resolved to be an intrinsic function
  (resp. subroutine) is used as a subroutine (resp. function).
  Lowering was attempted while the evaluate::Expression for the
  call was missing without any errors.

1 behavior change:

- Do not implicitly resolve subroutines (resp. functions) as intrinsics
  because their name is the name of an intrinsic function (resp.
  subroutine). Add justification in documentation.

Reviewed By: klausler, tskeith

Differential Revision: https://reviews.llvm.org/D90049

Try to fix buildbots after d3205bbca3e0002d76282878986993e7e7994779

[lldb] [Process/FreeBSDRemote] Fix #include for i386 compat

Include <x86/fpu.h> rather than <machine/fpu.h>, as the latter is not
present on i386.

Differential Revision: https://reviews.llvm.org/D90128

[lldb] [test/Register] Use initial state for write tests

Reset registers to their 'initial' state instead of a semi-random
pattern in write tests.  While the latter might have been helpful
while debugging failures (i.e. to distinguish unmodified registers
from mistakenly written zeroes), the former makes it possible to test
whether xstate_bv field is written correctly when using XSAVE.

With this change, the four relevant tests start failing on NetBSD
without D90105.

Differential Revision: https://reviews.llvm.org/D90114

[lldb] [Process/NetBSD] Set xs_xstate_bv correctly when setting regs

Ensure that xs_xstate_bv is set correctly before calling
WriteRegisterSet().  The bit can be clear if the relevant registers
were at their initial state when they were read, and it needs to be set
in order to apply changes from the XState structure.

Differential Revision: https://reviews.llvm.org/D90105

[lldb] [Process/Linux] Reuse NativeRegisterContextWatchpoint_x86

Differential Revision: https://reviews.llvm.org/D90119

[lldb] Fix bitfield "frame var" for pointers (pr47743)

Displaying large packed bitfields did not work if one was accessing them
through a pointer, and he used the "->" notation ("[0]." notation is
fine). The reason for that is that implicit dereference in -> is plumbed
all the way down to ValueObjectChild::UpdateValue, where the process of
fetching the child value was forked for this flag. The bitfield
"sliding" code was implemented only for the branch which did not require
dereferencing.

This patch restructures the function to avoid this mistake. Processing
now happens in two stages.
- first the parent is dereferenced (if needed)
- then the child value is computed (this step includes sliding and is
  common for both branches)

Differential Revision: https://reviews.llvm.org/D89236

[lldb] Modernize PseudoTerminal::Fork

[NFC][InstrRefLDV] Fix a typo

[llvm-mca] Add few memory instructions to cortex-a57 test

tsan: add mips64 support in lib/tsan/go/buildgo.sh

Enable mips64 support in buildgo.sh.

Author: mzh (Meng Zhuo)
Reviewed-in: https://reviews.llvm.org/D90130

[InstCombine] Add rotate tests where the shift amount is zero extended after masking

[InstCombine] Add support for zext(and(neg(amt),width-1)) rotate shift amount patterns

Alive2: https://alive2.llvm.org/ce/z/bCvvHd

[clang] Suppress "follow-up" diagnostics on recovery call expressions.

Because of typo-correction, the AST can be transformed, and the transformed
AST is marginally useful for diagnostics purpose, the following
diagnostics usually do harm than good (easily cause confusions).

Given the following code:

```
void abcc();
void test() {
  if (abc());
  // diagnostic 1 (for the typo-correction): the typo is correct to `abcc()`, so the code is treate as `if (abcc())` in AST perspective;
  // diagnostic 2 (for mismatch type): we perform an type-analysis on `if`, discover the type is not match
}
```

The secondary diagnostic "convertable to bool" is likely bogus to users.

The idea is to use RecoveryExpr (clang's dependent mechanism) to preserve the
recovery behavior but suppress all follow-up diagnostics.

Differential Revision: https://reviews.llvm.org/D89946

[MLIR][mlir-spirv-cpu-runner] A pass to emulate a call to kernel in LLVM

This patch introduces a pass for running
`mlir-spirv-cpu-runner` - LowerHostCodeToLLVMPass.

This pass emulates `gpu.launch_func` call in LLVM dialect and lowers
the host module code to LLVM. It removes the `gpu.module`, creates a
sequence of global variables that are later linked to the varables
in the kernel module, as well as a series of copies to/from
them to emulate the memory transfer to/from the host or to/from the
device sides. It also converts the remaining Standard dialect into
LLVM dialect, emitting C wrappers.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D86112

[clang-fuzzer] CreateAndRunJITFunc - fix use after move static analyzer warning.

We were using the unique_ptr M to determine the triple after it had been moved in the EngineBuilder constructor.

[llvm-ar][Object] Fix detection of need for 64-bit archive symbol tables

The code to detect the requirement for 64-bit offsets in the archive
symbol table was not correctly accounting for the archive file signature
and the size of all the contents of the symbol table itself, e.g. the
symbol table's header and string table. Also was not considering the
variation in symbol table formats. This could result in the creation of
large archives with a corrupt symbol table.

Change the testing environment variable SYM64_THRESHOLD to be an
absolute value rather than a power of 2 in order to enable precise
testing of this detection code.

Differential Revision: https://reviews.llvm.org/D89891

[DAGCombine] Add test case showing incorrect DAGCombine optimization

This optmization produces incorrect results when the vector element type
is not byte-sized. Related to D78568.

[MLIR][mlir-spirv-cpu-runner] A SPIR-V cpu runner prototype

This patch introduces a SPIR-V runner. The aim is to run a gpu
kernel on a CPU via GPU -> SPIRV -> LLVM conversions. This is a first
prototype, so more features will be added in due time.

- Overview
The runner follows similar flow as the other runners in-tree. However,
having converted the kernel to SPIR-V, we encode the bind attributes of
global variables that represent kernel arguments. Then SPIR-V module is
converted to LLVM. On the host side, we emulate passing the data to device
by creating in main module globals with the same symbolic name as in kernel
module. These global variables are later linked with ones from the nested
module. We copy data from kernel arguments to globals, call the kernel
function from nested module and then copy the data back.

- Current state
At the moment, the runner is capable of running 2 modules, nested one in
another. The kernel module must contain exactly one kernel function. Also,
the runner supports rank 1 integer memref types as arguments (to be scaled).

- Enhancement of JitRunner and ExecutionEngine
To translate nested modules to LLVM IR, JitRunner and ExecutionEngine were
altered to take an optional (default to `nullptr`) function reference that
is a custom LLVM IR module builder. This allows to customize LLVM IR module
creation from MLIR modules.

Reviewed By: ftynse, mravishankar

Differential Revision: https://reviews.llvm.org/D86108

[clangd] Fix remote index build failures due to lack of proto dependency

Previous attempt (15f6bad6d74a993e366c8fc93a9c91f213ac6bc3) introduced
add_dependencies but unfortunately it does not actually add a dependency
between RemoteIndexProto and RemoteIndexServiceProto. This is likely due
to some requirements of it that clang_add_library violates.

As a workaround, we will link RemoteIndexProto library to
RemoteIndexServiceProto which is logical because the library can not be
without linking to RemoteIndexProto anyway.

[LV] Add cost-model test for AArch64 select costs.

Currently, the cost of some compare/select patterns is overestimated on
AArch64.

[AMDGPU] Make more use of printNamedBit in AMDGPUInstPrinter. NFC.

[InstCombine] Add bswap test pattern using bitreverse intrinsic

This is mainly to help with future better bitreverse folding support but we can test it via bswap matching for now.

[lldb][NFC] Make GetShellSafeArgument simpler and faster

Escaping by inserting characters in the middle of a std::string isn't cheap.
It's much more verbose than just prepending a backslash in a loop.

[clangd] NFC: Update FIXME comment regarding lack of c/dtor support

Both `SymbolKind` and `indexSymbolKindToSymbolKind` support constructors and
separate them into a different category from regular methods.

Reviewed By: kadircet

Differential Revision: https://reviews.llvm.org/D89935

[InstCombine] collectBitParts - add bitreverse intrinsic support.

Fix SBError::SetErrorToGenericError

`SBError::SetErrorToGenericError` should call `Status::SetErrorToGenericError`,
not `Status::SetErrorToErrno`.

Reviewed By: teemperor

Differential Revision: https://reviews.llvm.org/D90151

[TableGen] [tests] Change integer ranges to use new '...' punctuation

Differential Revision: https://reviews.llvm.org/D90057

[analyzer] [NFC] Simplify SVal::getAsLocSymbol function using existing functions

Summary: Method of obtaining MemRegion from LocAsInteger/MemRegionVal already exists in SVal::getAsRegion function. Replace repetitive conditions in SVal::getAsLocSymbol with SVal::getAsRegion function.

Differential Revision: https://reviews.llvm.org/D89982

[VE] Support atomic store

Support atomic store instructions and add a regression test.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90137

[VE] Add vector logical instructions

Add VAND/VOR/VXOE/VEQV/VLDZ/VPCNT/VBRV/VSEQ instrucitons and regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90141

[VE] Add vector shift instructions

Add VSLL/VSLD/VSRL/VSLA/VSLAX/VSRA/VSRAX/VSFA instructionss.  Add
additonal AsmParser for VSLD special operand.  Also add regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90143

[X86] Use mtriple instead of march in MIR tests

[AArch64] Add 2 cases where insertelement lowering could be improved.

[OpenMP] changing OMP rtl to use shared memory instead of env variable

Patch by Erdner, Todd <todd.erdner@intel.com>

Differential Revision: https://reviews.llvm.org/D89898

[InstCombine] Add bswap test pattern using truncates

[libc++] Add a CI jobs to test the Standalone builds

[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination

The modified code in visitSTORE was missing a scalable vector check, and still
using the now deprecated implicit cast of TypeSize to uint64_t through the
overloaded operator. This patch fixes these issues.

This brings the logic in line with the comment on the context line immediately
above the added precondition.

Add a test in Redundantstores.ll that the warning is not triggered.

Revert "[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination"

This reverts commit 4604441386dc5fcd3165f4b39f5fa2e2c600f1bc.

Reverting because it was not the intended version of the patch, which
follows this patch.

[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination

The modified code in visitSTORE was missing a scalable vector check, and still
using the now deprecated implicit cast of TypeSize to uint64_t through the
overloaded operator. This patch fixes these issues.

This brings the logic in line with the comment on the context line immediately
above the added precondition.

Add a test in sve-redundant-store.ll that the warning is not triggered.

Differential Revision: https://reviews.llvm.org/D89701

Unconfuse gcc5.3 after 2e204e23911b1f / D87528

The local variable CmpResult added in that change shadowed the
type CmpResult, which confused an older gcc. Rename the variable
CmpResult to APFloatCmpResult.

[libc++] Fix indentation of buildkite-pipeline.yml

[lld][ELF] Don't write output to the test directory. NFC.

[clang][unittest] Don't hardcode the string "Assertion"

This depends on the libc implementation. Use the string from the
assertion message instead. Overly specific, but so is this entire test.

[AMDGPU] Avoid unused variable warning in Release builds. NFC.

SIRegisterInfo.cpp:480:19: error: unused variable 'SOffset'

Fix issue in cortex-a57 sched model

Differential revision: https://reviews.llvm.org/D90152

[mlir][Linalg] Add basic support for TileAndFuse on Linalg on tensors.

This revision allows the fusion of the producer of input tensors in the consumer under a tiling transformation (which produces subtensors).
Many pieces are still missing (e.g. support init_tensors, better refactor LinalgStructuredOp interface support, try to merge implementations and reuse code) but this still allows getting started.

The greedy pass itself is just for testing purposes and will be extracted in a separate test pass.

Differential revision: https://reviews.llvm.org/D89491

[ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90150

[lldb][PDB] Add ObjectFile PDB plugin

To allow loading PDB file with `target symbols add` command.

Differential Revision: https://reviews.llvm.org/D89812

[DebugInfo][dexter] Add dexter tests for escaped locals

Recently there has been renewed interest in improving debug-info for variables
that (partially or otherwise) live on the stack in optimised code.

At the moment instcombine speculates that stack slots are probably going to be
promoted to registers, and prepares the debug-info accordingly. It runs a
function called LowerDbgDeclare which converts dbg.declares to a set of
dbg.values after loads, and before stores and calls. Sometimes the stack
location remains (e.g. for escaped locals). If any dbg.values become undef
where the stack location is still valid we end up unnecessarily reducing
variable location coverage due to our inability to track multiple locations
simultaneously. There is a flag to disable this feature
(-instcombine-lower-dbg-declare=0), which prevents this conversion at the cost
of sometimes providing incorrect location info in the face of DSE, DCE, GVN,
CSE etc.

This has been discussed fairly extensively on PR34136.

The idea of these tests is to provide examples of situations that we should
consider when designing a new system, to aid discussions and eventually help
evaluate the implementation.

Dexter isn't ideal for observing specific optimisation behaviour. Writing an
exaustive test suite would be difficult, and the resultant suite would be
fragile. However, I think having some concrete executable examples is useful
at least as a reference.

Differential Revision: https://reviews.llvm.org/D89543

[SVE][AArch64] Fix TypeSize warning in loop vectorization legality

The warning would fire when calling isDereferenceableAndAlignedInLoop
with a scalable load. Calling isDereferenceableAndAlignedInLoop with a
scalable load would result in the use of the now deprecated implicit
cast of TypeSize to uint64_t through the overloaded operator.

This patch fixes this issue by:

- no longer considering vector loads as candidates in
  canVectorizeWithIfConvert. This doesn't make sense in the context of
  identifying scalar loads to vectorize.

- making use of getFixedSize inside isDereferenceableAndAlignedInLoop --
  this removes the dependency on the deprecated interface, and will
  trigger an assertion error if the function is ever called with a
  scalable type.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D89798

[SVE][AArch64] Fix TypeSize warning in GEP cost analysis

The warning would fire when calling getGEPCost for analyzing the cost of
a GEP instruction. This would result in the use of the now deprecated
implicit cast of TypeSize to uint64_t through the overloaded operator.

This patch fixes the issue by using getKnownMinSize instead of the
implicit cast. This is possible because the code is already
scalable-vector aware. The semantic behaviour of the code is unchanged
by this patch.

Reviewed By: sdesmalen, fpetrogalli

Differential Revision: https://reviews.llvm.org/D89872

[SVE][InstCombine] Fix TypeSize warning in canReplaceGEPIdxWithZero

The warning would fire when calling canReplaceGEPIdxWithZero on a GEP
whose source element type is a scalable vector. The size of scalable
vector types is not known, so this optimization cannot be performed.

This patch fixes the issue by:

- bailing out early in this routine if the GEP instruction's source
  element type is a scalable vector.

- making use of getFixedSize -- this removes the dependency on the
  deprecated interface.

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D89968

[SVE] Fix TypeSize warning in llvm::getGEPInductionOperand

We do not need to use the implicit cast here. We can instead can rely on
a comparison between two TypeSize objects instead. This algorithm will
work fine with scalable vectors.

Reviewed By: DavidTruby

Differential Revision: https://reviews.llvm.org/D90146

[mlir][vector] Update doc strings for insert_map/extract_map and fix insert_map semantic

Based on discourse discussion, fix the doc string and remove examples with
wrong semantic. Also fix insert_map semantic by adding missing operand for
vector we are inserting into.

Differential Revision: https://reviews.llvm.org/D89563

[AArch64] Extend tests for insertelement improvements.

Extends the tests added in a562dc82a8d9488d35ff535302716141bc6feaa3 to
cover more vector variants.

SourceManager: Return non-const references in getOrCreateContentCache and related, NFC

Update a few APIs to return non-const references instead of pointers,
and remove associated `const_cast`s and non-null assertions.

Differential Revision: https://reviews.llvm.org/D90067

[libc++abi] Make sure we can run the tests in Standalone mode

The tests would previously fail if the `python` executable wasn't found,
because we were missing the mandatory find_package.