SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [X86] Don't disassemble wbinvd with 0xf2 or 0x66 prefix. (details)
  2. [AMDGPU] Avoid offset register in MUBUF for direct stack object accesses (details)
  3. [clangd] Add dependency on remote index service proto (details)
  4. [IndVars] Use contextual knowledge when proving trivial conds (details)
  5. [NFC] Factor out common code into lambda for further improvement (details)
  6. [NFC] Remove unused funciton param (details)
  7. Fix broken build after previous commit (details)
  8. [VE] Support atomic fence (details)
  9. [Schedule] Add a MultiHazardRecognizer (details)
  10. [gn build] Port 61bc18de0b2 (details)
  11. [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate (details)
  12. [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate (details)
  13. [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred (details)
  14. [VE] Support atomic load (details)
  15. [PowerPC] Add test case for pr47830. NFC. (details)
  16. [ARM][SchedModels] Rename and generalize predicate. NFC (details)
  17. [AMDGPU] Emit new pal metadata by default (details)
  18. [AsmPrinter] Add per BB instruction mix remark. (details)
  19. [VE] Add integer arithmetic vector instructions (details)
  20. [VE] Add vector comparison and min/max (details)
  21. [Annotation] Allows annotation to carry some additional constant arguments. (details)
  22. [flang] Tighten rules to resolve procedure as intrinsic procedure (details)
  23. Try to fix buildbots after d3205bbca3e0002d76282878986993e7e7994779 (details)
  24. [lldb] [Process/FreeBSDRemote] Fix #include for i386 compat (details)
  25. [lldb] [test/Register] Use initial state for write tests (details)
  26. [lldb] [Process/NetBSD] Set xs_xstate_bv correctly when setting regs (details)
  27. [lldb] [Process/Linux] Reuse NativeRegisterContextWatchpoint_x86 (details)
  28. [lldb] Fix bitfield "frame var" for pointers (pr47743) (details)
  29. [lldb] Modernize PseudoTerminal::Fork (details)
  30. [NFC][InstrRefLDV] Fix a typo (details)
  31. [llvm-mca] Add few memory instructions to cortex-a57 test (details)
  32. tsan: add mips64 support in lib/tsan/go/buildgo.sh (details)
  33. [InstCombine] Add rotate tests where the shift amount is zero extended after masking (details)
  34. [InstCombine] Add support for zext(and(neg(amt),width-1)) rotate shift amount patterns (details)
  35. [clang] Suppress "follow-up" diagnostics on recovery call expressions. (details)
  36. [MLIR][mlir-spirv-cpu-runner] A pass to emulate a call to kernel in LLVM (details)
  37. [clang-fuzzer] CreateAndRunJITFunc - fix use after move static analyzer warning. (details)
  38. [llvm-ar][Object] Fix detection of need for 64-bit archive symbol tables (details)
  39. [DAGCombine] Add test case showing incorrect DAGCombine optimization (details)
  40. [MLIR][mlir-spirv-cpu-runner] A SPIR-V cpu runner prototype (details)
  41. [clangd] Fix remote index build failures due to lack of proto dependency (details)
  42. [LV] Add cost-model test for AArch64 select costs. (details)
  43. [AMDGPU] Make more use of printNamedBit in AMDGPUInstPrinter. NFC. (details)
  44. [InstCombine] Add bswap test pattern using bitreverse intrinsic (details)
  45. [lldb][NFC] Make GetShellSafeArgument simpler and faster (details)
  46. [clangd] NFC: Update FIXME comment regarding lack of c/dtor support (details)
  47. [InstCombine] collectBitParts - add bitreverse intrinsic support. (details)
  48. Fix SBError::SetErrorToGenericError (details)
  49. [TableGen] [tests] Change integer ranges to use new '...' punctuation (details)
  50. [analyzer] [NFC] Simplify SVal::getAsLocSymbol function using existing functions (details)
  51. [VE] Support atomic store (details)
  52. [VE] Add vector logical instructions (details)
  53. [VE] Add vector shift instructions (details)
  54. [X86] Use mtriple instead of march in MIR tests (details)
  55. [AArch64] Add 2 cases where insertelement lowering could be improved. (details)
  56. [OpenMP] changing OMP rtl to use shared memory instead of env variable (details)
  57. [InstCombine] Add bswap test pattern using truncates (details)
  58. [libc++] Add a CI jobs to test the Standalone builds (details)
  59. [SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination (details)
  60. Revert "[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination" (details)
  61. [SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination (details)
  62. Unconfuse gcc5.3 after 2e204e23911b1f / D87528 (details)
  63. [libc++] Fix indentation of buildkite-pipeline.yml (details)
  64. [lld][ELF] Don't write output to the test directory. NFC. (details)
  65. [clang][unittest] Don't hardcode the string "Assertion" (details)
  66. [AMDGPU] Avoid unused variable warning in Release builds. NFC. (details)
  67. Fix issue in cortex-a57 sched model (details)
  68. [mlir][Linalg] Add basic support for TileAndFuse on Linalg on tensors. (details)
  69. [ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate (details)
  70. [lldb][PDB] Add ObjectFile PDB plugin (details)
  71. [DebugInfo][dexter] Add dexter tests for escaped locals (details)
  72. [SVE][AArch64] Fix TypeSize warning in loop vectorization legality (details)
  73. [SVE][AArch64] Fix TypeSize warning in GEP cost analysis (details)
  74. [SVE][InstCombine] Fix TypeSize warning in canReplaceGEPIdxWithZero (details)
  75. [SVE] Fix TypeSize warning in llvm::getGEPInductionOperand (details)
  76. [mlir][vector] Update doc strings for insert_map/extract_map and fix insert_map semantic (details)
  77. [AArch64] Extend tests for insertelement improvements. (details)
  78. SourceManager: Return non-const references in getOrCreateContentCache and related, NFC (details)
  79. [libc++abi] Make sure we can run the tests in Standalone mode (details)
Commit 82974e0114f02ffc07557e217d87f8dc4e100a26 by craig.topper
[X86] Don't disassemble wbinvd with 0xf2 or 0x66 prefix.

The 0xf3 prefix has been defined as wbnoinvd on Icelake Server. So
the prefix isn't ignored by the CPU. AMD documentation suggests that
wbnoinvd is treated as wbinvd on older processors. Intel documentation
is not clear. Perhaps 0xf2 and 0x66 are treated the same, but its
not documented.

This patch changes TB to PS in the td file so 0xf2 and 0x66 will
be treated as errors. This matches versions of objdump after
wbnoinvd was added.
The file was modifiedllvm/lib/Target/X86/X86InstrSystem.td
The file was addedllvm/test/MC/Disassembler/X86/invalid-wbinvd.txt
The file was modifiedllvm/test/MC/Disassembler/X86/x86-64.txt
The file was modifiedllvm/test/MC/Disassembler/X86/x86-32.txt
Commit 5a061041ec4c8e16ba8d8321353d3a35ca77858f by Christudasan.Devadasan
[AMDGPU] Avoid offset register in MUBUF for direct stack object accesses

We use an absolute address for stack objects and
it would be necessary to have a constant 0 for soffset field.

Fixes: SWDEV-228562

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D89234
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/call-argument-types.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
Commit 15f6bad6d74a993e366c8fc93a9c91f213ac6bc3 by kbobyrev
[clangd] Add dependency on remote index service proto

It requires Index.proto to be built first. Failed builds:
https://github.com/clangd/clangd/runs/1305985916
The file was modifiedclang-tools-extra/clangd/index/remote/CMakeLists.txt
Commit c019099053c147c6fb924a88e30c0993144ce22e by mkazantsev
[IndVars] Use contextual knowledge when proving trivial conds

No exact example where it would help, but it's a generally a more
powerful way to prove predicates.
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
Commit 4b5e848befdf786f5c905adf3b6c589216a24bff by mkazantsev
[NFC] Factor out common code into lambda for further improvement
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
Commit cdccc82f4825a1c9ac1bc0df2a222acdf5e820d4 by mkazantsev
[NFC] Remove unused funciton param
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
Commit bfabd7878b3240732d64b09eeadbc1eccc21910a by mkazantsev
Fix broken build after previous commit
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
Commit 52f03fe1151f65278c855651bb8f325cca8500ea by marukawa
[VE] Support atomic fence

Support atomic fence instruction and add a regression test.
Add MEMBARRIER pseudo insturction also to use it as a barrier
against to the compiler optimizations.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90112
The file was modifiedllvm/lib/Target/VE/VEISelLowering.h
The file was addedllvm/test/CodeGen/VE/atomic_fence.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was modifiedllvm/lib/Target/VE/VEISelLowering.cpp
Commit 61bc18de0b2edf8659053b06d73dfd2563143572 by david.green
[Schedule] Add a MultiHazardRecognizer

This adds a MultiHazardRecognizer and starts to make use of it in the
ARM backend. The idea of the class is to allow multiple independent
hazard recognizers to be added to a single base MultiHazardRecognizer,
allowing them to all work in parallel without requiring them to be
chained into subclasses. They can then be added or not based on cpu or
subtarget features, which will become useful in the ARM backend once
more hazard recognizers are being used for various things.

This also renames ARMHazardRecognizer to ARMHazardRecognizerFPMLx in the
process, to more clearly explain what that recognizer is designed for.

Differential Revision: https://reviews.llvm.org/D72939
The file was modifiedllvm/lib/Target/ARM/ARMHazardRecognizer.cpp
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was addedllvm/include/llvm/CodeGen/MultiHazardRecognizer.h
The file was addedllvm/lib/CodeGen/MultiHazardRecognizer.cpp
The file was modifiedllvm/lib/Target/ARM/ARMHazardRecognizer.h
Commit 8000d277bafa15f52061961e1ff1020306487e38 by llvmgnsyncbot
[gn build] Port 61bc18de0b2
The file was modifiedllvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Commit d613e39d52d263823324a695614c3c2981e94927 by eleviant
[ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90045
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMSchedule.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
The file was modifiedllvm/include/llvm/Target/TargetInstrPredicate.td
Commit a4fc18e6410f1d88ef3171e4eb6afc33d750f69a by eleviant
[ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90029
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
The file was modifiedllvm/lib/Target/ARM/ARMSchedule.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
Commit 99b2756517f23252d1bd60f2a15c5799df054ef3 by eleviant
[ARM][SchedModels] Get rid of IsLdrAm2ScaledPred

Differential revision: https://reviews.llvm.org/D90024
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
Commit f32992ad24470e0abfc310dcd62359f35378be7b by marukawa
[VE] Support atomic load

Support atomic load instruction and add a regression test.
VE uses release consitency, so need to insert fence around
atomic instructions.  This patch enable AtomicExpandPass
and use emitLeadingFence and emitTrailingFence mechanism
for such purpose.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90135
The file was modifiedllvm/lib/Target/VE/VEISelLowering.cpp
The file was modifiedllvm/lib/Target/VE/VEISelLowering.h
The file was addedllvm/test/CodeGen/VE/atomic_load.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was modifiedllvm/lib/Target/VE/VETargetMachine.cpp
Commit 82150dae8660c005823ed2da5c86cc1559a40c7b by lkail
[PowerPC] Add test case for pr47830. NFC.
The file was addedllvm/test/CodeGen/PowerPC/pr47830.ll
Commit a95ce5f65f13608f652d554ee37e61d9df7fa0d3 by eleviant
[ARM][SchedModels] Rename and generalize predicate. NFC
The file was modifiedllvm/lib/Target/ARM/ARMSchedule.td
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
Commit a094b4fa4b7f00d3e389a55c401e4078534494b8 by sebastian.neubauer
[AMDGPU] Emit new pal metadata by default

If no pal metadata is given, default to the msgpack format instead of
the legacy metadata. This makes tests better readable.

Differential Revision: https://reviews.llvm.org/D90035
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-vs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-ls.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-es.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-gs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-cs.ll
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/elf-notes.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-hs.ll
Commit b2bec7cece9bb7d17799ac0af65a770cab4397ee by flo
[AsmPrinter] Add per BB instruction mix remark.

This patch adds a remarks that provides counts for each opcode per basic block.

An snippet of the generated information can be seen below.

The current implementation uses the target specific opcode for the counts. For example, on AArch64 this means we currently get 2 entries for `add` instructions if the block contains 32 and 64 bit adds. Similarly, immediate version are treated differently.

Unfortunately there seems to be no convenient way to get only the mnemonic part of the instruction as a string AFAIK. This could be improved in the future.

```
--- !Analysis
Pass:            asm-printer
Name:            InstructionMix
DebugLoc:        { File: arm64-instruction-mix-remarks.ll, Line: 30, Column: 30 }
Function:        foo
Args:
  - String:          'BasicBlock: '
  - BasicBlock:      else
  - String:          "\n"
  - String:          INST_MADDWrrr
  - String:          ': '
  - INST_MADDWrrr:   '2'
  - String:          "\n"
  - String:          INST_MOVZWi
  - String:          ': '
  - INST_MOVZWi:     '1'
```

Reviewed By: anemet, thegameg, paquette

Differential Revision: https://reviews.llvm.org/D89892
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was addedllvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
Commit 0acf7002433052c02487645759540431c3b94829 by marukawa
[VE] Add integer arithmetic vector instructions

Add VADD/VADS/VADX/VSUB/VSBS/VSBX/VMPY/VMPS/VMPX/VMPD/VDIV/VDVS/VDVX
instructions.  Also add regression tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89642
The file was addedllvm/test/MC/VE/VMPS.s
The file was modifiedllvm/lib/Target/VE/VEInstrVec.td
The file was addedllvm/test/MC/VE/VMPD.s
The file was addedllvm/test/MC/VE/VSBS.s
The file was addedllvm/test/MC/VE/VMPX.s
The file was addedllvm/test/MC/VE/VADS.s
The file was addedllvm/test/MC/VE/VSBX.s
The file was addedllvm/test/MC/VE/VDVX.s
The file was addedllvm/test/MC/VE/VDVS.s
The file was addedllvm/test/MC/VE/VMPY.s
The file was addedllvm/test/MC/VE/VADX.s
The file was addedllvm/test/MC/VE/VDIV.s
The file was addedllvm/test/MC/VE/VADD.s
The file was addedllvm/test/MC/VE/VSUB.s
Commit 8aa60f67dc8c67390680b7a3be0d31384300f09f by marukawa
[VE] Add vector comparison and min/max

Add VCMP/VCPS/VCPX/VCMS/VCMX vector instructions.  Also add regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89643
The file was modifiedllvm/lib/Target/VE/VEInstrVec.td
The file was addedllvm/test/MC/VE/VCMP.s
The file was addedllvm/test/MC/VE/VCPX.s
The file was addedllvm/test/MC/VE/VCMS.s
The file was addedllvm/test/MC/VE/VCMX.s
The file was addedllvm/test/MC/VE/VCPS.s
Commit d3205bbca3e0002d76282878986993e7e7994779 by tyker
[Annotation] Allows annotation to carry some additional constant arguments.

This allows using annotation in a much more contexts than it currently has.
especially when annotation with template or constexpr.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D88645
The file was modifiedclang/test/Parser/objc-implementation-attrs.m
The file was modifiedllvm/test/Analysis/CostModel/X86/free-intrinsics.ll
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
The file was addedclang/test/CodeGenCXX/attr-annotate.cpp
The file was modifiedclang/test/Sema/annotate.c
The file was modifiedclang/test/Misc/pragma-attribute-cxx.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.h
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was addedclang/test/CodeGenCXX/attr-annotate2.cpp
The file was modifiedclang/test/Misc/pragma-attribute-objc.m
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedclang/test/Parser/access-spec-attrs.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/test/CodeGen/annotations-var.c
The file was modifiedclang/test/CodeGen/annotations-loc.c
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/include/clang/Sema/ParsedAttr.h
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/test/CodeGen/annotations-global.c
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
The file was addedclang/test/SemaCXX/attr-annotate.cpp
The file was modifiedllvm/test/Analysis/CostModel/free-intrinsics-datalayout.ll
The file was modifiedllvm/test/Analysis/CostModel/free-intrinsics-no_info.ll
The file was modifiedclang/test/AST/ast-dump-attr.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/CodeGen/annotations-field.c
The file was modifiedllvm/test/Transforms/InstCombine/assume_inevitable.ll
The file was modifiedclang/test/Sema/pragma-attribute.c
The file was modifiedllvm/test/CodeGen/Generic/ptr-annotate.ll
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
Commit 878b526409acb04b11f0a6b83c561bfee3521e57 by jperier
[flang] Tighten rules to resolve procedure as intrinsic procedure

2 Bug fixes:

- Do not resolve procedure as intrinsic if they appeared in an
  EXTERNAL attribute statement (one path was not considering this flag)

- Emit an error if a procedure resolved to be an intrinsic function
  (resp. subroutine) is used as a subroutine (resp. function).
  Lowering was attempted while the evaluate::Expression for the
  call was missing without any errors.

1 behavior change:

- Do not implicitly resolve subroutines (resp. functions) as intrinsics
  because their name is the name of an intrinsic function (resp.
  subroutine). Add justification in documentation.

Reviewed By: klausler, tskeith

Differential Revision: https://reviews.llvm.org/D90049
The file was addedflang/test/Semantics/symbol19.f90
The file was modifiedflang/lib/Semantics/resolve-names.cpp
The file was modifiedflang/lib/Evaluate/intrinsics.cpp
The file was modifiedflang/include/flang/Evaluate/intrinsics.h
The file was addedflang/test/Semantics/call16.f90
The file was modifiedflang/docs/Intrinsics.md
Commit 4afa077899b1e3def4cff475deae73681db04e21 by tyker
Try to fix buildbots after d3205bbca3e0002d76282878986993e7e7994779
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
Commit 7acf2e2e1e8f7e2eac2dd5bbf7d752ba7ad4e79c by mgorny
[lldb] [Process/FreeBSDRemote] Fix #include for i386 compat

Include <x86/fpu.h> rather than <machine/fpu.h>, as the latter is not
present on i386.

Differential Revision: https://reviews.llvm.org/D90128
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
Commit 37d4d3bb4daf409102237132ae8e1db250da83be by mgorny
[lldb] [test/Register] Use initial state for write tests

Reset registers to their 'initial' state instead of a semi-random
pattern in write tests.  While the latter might have been helpful
while debugging failures (i.e. to distinguish unmodified registers
from mistakenly written zeroes), the former makes it possible to test
whether xstate_bv field is written correctly when using XSAVE.

With this change, the four relevant tests start failing on NetBSD
without D90105.

Differential Revision: https://reviews.llvm.org/D90114
The file was modifiedlldb/test/Shell/Register/Inputs/x86-ymm-write.cpp
The file was modifiedlldb/test/Shell/Register/Inputs/x86-64-write.cpp
The file was modifiedlldb/test/Shell/Register/Inputs/x86-mm-xmm-write.cpp
The file was modifiedlldb/test/Shell/Register/Inputs/x86-zmm-write.cpp
Commit a8902376651a7adbacd0c1934d9f70bdb9fad7f0 by mgorny
[lldb] [Process/NetBSD] Set xs_xstate_bv correctly when setting regs

Ensure that xs_xstate_bv is set correctly before calling
WriteRegisterSet().  The bit can be clear if the relevant registers
were at their initial state when they were read, and it needs to be set
in order to apply changes from the XState structure.

Differential Revision: https://reviews.llvm.org/D90105
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
Commit f5ca27569eacc398f0e4fc63a9b55cafac398c04 by mgorny
[lldb] [Process/Linux] Reuse NativeRegisterContextWatchpoint_x86

Differential Revision: https://reviews.llvm.org/D90119
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_s390x.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
Commit 97ca9ca180f0810adcc1637d1a6dd32a04f63cfe by pavel
[lldb] Fix bitfield "frame var" for pointers (pr47743)

Displaying large packed bitfields did not work if one was accessing them
through a pointer, and he used the "->" notation ("[0]." notation is
fine). The reason for that is that implicit dereference in -> is plumbed
all the way down to ValueObjectChild::UpdateValue, where the process of
fetching the child value was forked for this flag. The bitfield
"sliding" code was implemented only for the branch which did not require
dereferencing.

This patch restructures the function to avoid this mistake. Processing
now happens in two stages.
- first the parent is dereferenced (if needed)
- then the child value is computed (this step includes sliding and is
  common for both branches)

Differential Revision: https://reviews.llvm.org/D89236
The file was modifiedlldb/test/API/lang/c/bitfields/TestBitfields.py
The file was modifiedlldb/test/API/lang/c/bitfields/main.c
The file was modifiedlldb/source/Core/ValueObjectChild.cpp
Commit e4cc6e9bcdff5fe979ab72025cb803d723cd9c31 by pavel
[lldb] Modernize PseudoTerminal::Fork
The file was modifiedlldb/source/Host/common/PseudoTerminal.cpp
The file was modifiedlldb/include/lldb/Host/PseudoTerminal.h
The file was modifiedlldb/source/Plugins/Process/FreeBSD/ProcessMonitor.cpp
Commit a64b2c93662d8c9bbe49561980ed6c78892491d3 by djtodoro
[NFC][InstrRefLDV] Fix a typo
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
Commit 1876d06ea31f38411012841971a3ff69b4a864d4 by eleviant
[llvm-mca] Add few memory instructions to cortex-a57 test
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
Commit 5cad535ccfebf9b41a57cf2788d8de7a765f7f35 by dvyukov
tsan: add mips64 support in lib/tsan/go/buildgo.sh

Enable mips64 support in buildgo.sh.

Author: mzh (Meng Zhuo)
Reviewed-in: https://reviews.llvm.org/D90130
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
The file was modifiedcompiler-rt/lib/tsan/go/buildgo.sh
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_platform.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform.h
Commit 821f3b763ae506b329144550028a4fd0cba0a361 by llvm-dev
[InstCombine] Add rotate tests where the shift amount is zero extended after masking
The file was modifiedllvm/test/Transforms/InstCombine/rotate.ll
Commit 6b2eb31e1e2db1f3ca7a5c4914ab08cb18698de7 by llvm-dev
[InstCombine] Add support for zext(and(neg(amt),width-1)) rotate shift amount patterns

Alive2: https://alive2.llvm.org/ce/z/bCvvHd
The file was modifiedllvm/test/Transforms/InstCombine/rotate.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit efa9aaad703e6b150980ed1a74b4e7c9da7d85a2 by hokein.wu
[clang] Suppress "follow-up" diagnostics on recovery call expressions.

Because of typo-correction, the AST can be transformed, and the transformed
AST is marginally useful for diagnostics purpose, the following
diagnostics usually do harm than good (easily cause confusions).

Given the following code:

```
void abcc();
void test() {
  if (abc());
  // diagnostic 1 (for the typo-correction): the typo is correct to `abcc()`, so the code is treate as `if (abcc())` in AST perspective;
  // diagnostic 2 (for mismatch type): we perform an type-analysis on `if`, discover the type is not match
}
```

The secondary diagnostic "convertable to bool" is likely bogus to users.

The idea is to use RecoveryExpr (clang's dependent mechanism) to preserve the
recovery behavior but suppress all follow-up diagnostics.

Differential Revision: https://reviews.llvm.org/D89946
The file was modifiedclang/test/SemaCXX/typo-correction-delayed.cpp
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/test/AST/ast-dump-recovery.cpp
Commit cae4067ec1cdf7846aa46dab13d3bc1f58b76016 by antiagainst
[MLIR][mlir-spirv-cpu-runner] A pass to emulate a call to kernel in LLVM

This patch introduces a pass for running
`mlir-spirv-cpu-runner` - LowerHostCodeToLLVMPass.

This pass emulates `gpu.launch_func` call in LLVM dialect and lowers
the host module code to LLVM. It removes the `gpu.module`, creates a
sequence of global variables that are later linked to the varables
in the kernel module, as well as a series of copies to/from
them to emulate the memory transfer to/from the host or to/from the
device sides. It also converts the remaining Standard dialect into
LLVM dialect, emitting C wrappers.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D86112
The file was addedmlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
The file was addedmlir/test/Conversion/SPIRVToLLVM/lower-host-to-llvm-calls.mlir
The file was modifiedmlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt
The file was modifiedmlir/include/mlir/Conversion/Passes.td
Commit e4991867fb5ace434640bfacfd28720ad031d33c by llvm-dev
[clang-fuzzer] CreateAndRunJITFunc - fix use after move static analyzer warning.

We were using the unique_ptr M to determine the triple after it had been moved in the EngineBuilder constructor.
The file was modifiedclang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp
Commit 2add7c5cf3ebbba629d2756b3e91728e55b40881 by andrew.ng
[llvm-ar][Object] Fix detection of need for 64-bit archive symbol tables

The code to detect the requirement for 64-bit offsets in the archive
symbol table was not correctly accounting for the archive file signature
and the size of all the contents of the symbol table itself, e.g. the
symbol table's header and string table. Also was not considering the
variation in symbol table formats. This could result in the creation of
large archives with a corrupt symbol table.

Change the testing environment variable SYM64_THRESHOLD to be an
absolute value rather than a power of 2 in order to enable precise
testing of this detection code.

Differential Revision: https://reviews.llvm.org/D89891
The file was modifiedllvm/test/Object/archive-symtab.test
The file was modifiedllvm/lib/Object/ArchiveWriter.cpp
Commit ffa6d2afa4a6f35e2e99172a17d489bcec7f0353 by fraser
[DAGCombine] Add test case showing incorrect DAGCombine optimization

This optmization produces incorrect results when the vector element type
is not byte-sized. Related to D78568.
The file was addedllvm/test/CodeGen/AMDGPU/extract-load-i1.ll
Commit 89808ce7343b22586bfd0d3fafddcdbba94fbcbb by antiagainst
[MLIR][mlir-spirv-cpu-runner] A SPIR-V cpu runner prototype

This patch introduces a SPIR-V runner. The aim is to run a gpu
kernel on a CPU via GPU -> SPIRV -> LLVM conversions. This is a first
prototype, so more features will be added in due time.

- Overview
The runner follows similar flow as the other runners in-tree. However,
having converted the kernel to SPIR-V, we encode the bind attributes of
global variables that represent kernel arguments. Then SPIR-V module is
converted to LLVM. On the host side, we emulate passing the data to device
by creating in main module globals with the same symbolic name as in kernel
module. These global variables are later linked with ones from the nested
module. We copy data from kernel arguments to globals, call the kernel
function from nested module and then copy the data back.

- Current state
At the moment, the runner is capable of running 2 modules, nested one in
another. The kernel module must contain exactly one kernel function. Also,
the runner supports rank 1 integer memref types as arguments (to be scaled).

- Enhancement of JitRunner and ExecutionEngine
To translate nested modules to LLVM IR, JitRunner and ExecutionEngine were
altered to take an optional (default to `nullptr`) function reference that
is a custom LLVM IR module builder. This allows to customize LLVM IR module
creation from MLIR modules.

Reviewed By: ftynse, mravishankar

Differential Revision: https://reviews.llvm.org/D86108
The file was addedmlir/test/mlir-spirv-cpu-runner/mlir_test_spirv_cpu_runner_c_wrappers.cpp
The file was addedmlir/test/mlir-spirv-cpu-runner/simple_add.mlir
The file was modifiedmlir/test/lit.site.cfg.py.in
The file was modifiedmlir/tools/CMakeLists.txt
The file was modifiedmlir/include/mlir/ExecutionEngine/ExecutionEngine.h
The file was modifiedmlir/test/lit.cfg.py
The file was modifiedmlir/lib/ExecutionEngine/JitRunner.cpp
The file was modifiedmlir/test/CMakeLists.txt
The file was modifiedmlir/include/mlir/ExecutionEngine/JitRunner.h
The file was modifiedmlir/lib/ExecutionEngine/ExecutionEngine.cpp
The file was addedmlir/test/mlir-spirv-cpu-runner/double.mlir
The file was addedmlir/test/mlir-spirv-cpu-runner/CMakeLists.txt
The file was modifiedmlir/examples/toy/Ch6/toyc.cpp
The file was addedmlir/test/mlir-spirv-cpu-runner/lit.local.cfg
The file was modifiedmlir/examples/toy/Ch7/toyc.cpp
The file was modifiedmlir/CMakeLists.txt
The file was addedmlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
The file was addedmlir/tools/mlir-spirv-cpu-runner/CMakeLists.txt
Commit 58d0ef2d0466a893ab400f6a9829057b9d851038 by kbobyrev
[clangd] Fix remote index build failures due to lack of proto dependency

Previous attempt (15f6bad6d74a993e366c8fc93a9c91f213ac6bc3) introduced
add_dependencies but unfortunately it does not actually add a dependency
between RemoteIndexProto and RemoteIndexServiceProto. This is likely due
to some requirements of it that clang_add_library violates.

As a workaround, we will link RemoteIndexProto library to
RemoteIndexServiceProto which is logical because the library can not be
without linking to RemoteIndexProto anyway.
The file was modifiedclang-tools-extra/clangd/index/remote/CMakeLists.txt
Commit 1747aae9fc64448fb9b4f715dcd327c94f2fa4a6 by flo
[LV] Add cost-model test for AArch64 select costs.

Currently, the cost of some compare/select patterns is overestimated on
AArch64.
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/select-costs.ll
Commit 0ca4124798df6518bb7b3b3722e0ab788acdd494 by jay.foad
[AMDGPU] Make more use of printNamedBit in AMDGPUInstPrinter. NFC.
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
Commit 16f126df437f9ea19383c5486181c5e2797227f2 by llvm-dev
[InstCombine] Add bswap test pattern using bitreverse intrinsic

This is mainly to help with future better bitreverse folding support but we can test it via bswap matching for now.
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit d0ee1d8efe804b3184b1073cd367a307867f1372 by Raphael Isemann
[lldb][NFC] Make GetShellSafeArgument simpler and faster

Escaping by inserting characters in the middle of a std::string isn't cheap.
It's much more verbose than just prepending a backslash in a loop.
The file was modifiedlldb/source/Utility/Args.cpp
Commit 1704704e762f232e827849ee881ebe74b5db7ef1 by kbobyrev
[clangd] NFC: Update FIXME comment regarding lack of c/dtor support

Both `SymbolKind` and `indexSymbolKindToSymbolKind` support constructors and
separate them into a different category from regular methods.

Reviewed By: kadircet

Differential Revision: https://reviews.llvm.org/D89935
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
The file was modifiedclang-tools-extra/clangd/FindSymbols.cpp
Commit 532f3bec3e019a3e6089edf6bd21e9b9b540542b by llvm-dev
[InstCombine] collectBitParts - add bitreverse intrinsic support.
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 206e8d8905035f6e9049b97c9cd8af0eaa5aa118 by Raphael Isemann
Fix SBError::SetErrorToGenericError

`SBError::SetErrorToGenericError` should call `Status::SetErrorToGenericError`,
not `Status::SetErrorToErrno`.

Reviewed By: teemperor

Differential Revision: https://reviews.llvm.org/D90151
The file was addedlldb/test/API/python_api/sberror/TestSBError.py
The file was modifiedlldb/source/API/SBError.cpp
Commit 26e2e9f2de7efdfb843a5440e7a94c4e919efd7a by paul
[TableGen] [tests] Change integer ranges to use new '...' punctuation

Differential Revision: https://reviews.llvm.org/D90057
The file was modifiedllvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td
The file was modifiedllvm/test/TableGen/Common/reg-with-subregs-common.td
The file was modifiedllvm/test/TableGen/FixedLenDecoderEmitter/conflict.td
The file was modifiedllvm/unittests/TableGen/Automata.td
Commit 32efb81ea60a9e99571923bf9308598f6cd341f2 by dpetrov
[analyzer] [NFC] Simplify SVal::getAsLocSymbol function using existing functions

Summary: Method of obtaining MemRegion from LocAsInteger/MemRegionVal already exists in SVal::getAsRegion function. Replace repetitive conditions in SVal::getAsLocSymbol with SVal::getAsRegion function.

Differential Revision: https://reviews.llvm.org/D89982
The file was modifiedclang/lib/StaticAnalyzer/Core/SVals.cpp
Commit cfefef50c18a481040203f15b55edf89c1fafceb by marukawa
[VE] Support atomic store

Support atomic store instructions and add a regression test.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90137
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was addedllvm/test/CodeGen/VE/atomic_store.ll
Commit 83cb423c6e19f3aad819b89140b1d74203b23180 by marukawa
[VE] Add vector logical instructions

Add VAND/VOR/VXOE/VEQV/VLDZ/VPCNT/VBRV/VSEQ instrucitons and regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90141
The file was addedllvm/test/MC/VE/VAND.s
The file was addedllvm/test/MC/VE/VOR.s
The file was addedllvm/test/MC/VE/VLDZ.s
The file was addedllvm/test/MC/VE/VPCNT.s
The file was modifiedllvm/lib/Target/VE/VEInstrVec.td
The file was addedllvm/test/MC/VE/VSEQ.s
The file was addedllvm/test/MC/VE/VEQV.s
The file was addedllvm/test/MC/VE/VBRV.s
The file was addedllvm/test/MC/VE/VXOR.s
Commit 9d0db405b57b892d5dad75549dea942c337e9f0d by marukawa
[VE] Add vector shift instructions

Add VSLL/VSLD/VSRL/VSLA/VSLAX/VSRA/VSRAX/VSFA instructionss.  Add
additonal AsmParser for VSLD special operand.  Also add regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90143
The file was addedllvm/test/MC/VE/VSLA.s
The file was addedllvm/test/MC/VE/VSLL.s
The file was modifiedllvm/lib/Target/VE/VEInstrVec.td
The file was addedllvm/test/MC/VE/VSRAX.s
The file was modifiedllvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
The file was addedllvm/test/MC/VE/VSRA.s
The file was addedllvm/test/MC/VE/VSLAX.s
The file was addedllvm/test/MC/VE/VSFA.s
The file was addedllvm/test/MC/VE/VSLD.s
Commit 2030db328ae319b53c358923009f3d48d6fd4b52 by llvm-dev
[X86] Use mtriple instead of march in MIR tests
The file was modifiedllvm/test/CodeGen/X86/opt_phis.mir
The file was modifiedllvm/test/CodeGen/X86/opt_phis2.mir
The file was modifiedllvm/test/CodeGen/X86/unreachable-mbb-undef-phi.mir
The file was modifiedllvm/test/CodeGen/X86/x87-reg-usage.mir
Commit a562dc82a8d9488d35ff535302716141bc6feaa3 by flo
[AArch64] Add 2 cases where insertelement lowering could be improved.
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
Commit d6a0957467e86d5a87964d45fae18733e212c86f by Andrey.Churbanov
[OpenMP] changing OMP rtl to use shared memory instead of env variable

Patch by Erdner, Todd <todd.erdner@intel.com>

Differential Revision: https://reviews.llvm.org/D89898
The file was modifiedopenmp/runtime/cmake/config-ix.cmake
The file was modifiedopenmp/runtime/cmake/LibompHandleFlags.cmake
The file was modifiedopenmp/runtime/src/kmp_runtime.cpp
Commit 0ef6a25e195bafa285d3b957f247bfb23b2cf704 by llvm-dev
[InstCombine] Add bswap test pattern using truncates
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit d3024a074be09f6589eccac00cecabccd8258f2d by Louis Dionne
[libc++] Add a CI jobs to test the Standalone builds
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was modifiedlibcxx/utils/ci/run-buildbot.sh
The file was modifiedlibcxx/src/CMakeLists.txt
Commit 4604441386dc5fcd3165f4b39f5fa2e2c600f1bc by joe.ellis
[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination

The modified code in visitSTORE was missing a scalable vector check, and still
using the now deprecated implicit cast of TypeSize to uint64_t through the
overloaded operator. This patch fixes these issues.

This brings the logic in line with the comment on the context line immediately
above the added precondition.

Add a test in Redundantstores.ll that the warning is not triggered.
The file was modifiedllvm/test/CodeGen/AArch64/Redundantstore.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 6536d6040f5cd20d554901e265519b80dd8119f2 by peter.waller
Revert "[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination"

This reverts commit 4604441386dc5fcd3165f4b39f5fa2e2c600f1bc.

Reverting because it was not the intended version of the patch, which
follows this patch.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/AArch64/Redundantstore.ll
Commit 5b742a0c106fbed11779d6dd99854a6f97643524 by peter.waller
[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination

The modified code in visitSTORE was missing a scalable vector check, and still
using the now deprecated implicit cast of TypeSize to uint64_t through the
overloaded operator. This patch fixes these issues.

This brings the logic in line with the comment on the context line immediately
above the added precondition.

Add a test in sve-redundant-store.ll that the warning is not triggered.

Differential Revision: https://reviews.llvm.org/D89701
The file was addedllvm/test/CodeGen/AArch64/sve-redundant-store.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit c686dfd61705f33419875b22eb08bd197a72cd18 by thakis
Unconfuse gcc5.3 after 2e204e23911b1f / D87528

The local variable CmpResult added in that change shadowed the
type CmpResult, which confused an older gcc. Rename the variable
CmpResult to APFloatCmpResult.
The file was modifiedclang/lib/AST/ExprConstant.cpp
Commit 88374f76ee19d21b2c64425c95f05a20d37a84fa by Louis Dionne
[libc++] Fix indentation of buildkite-pipeline.yml
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
Commit 85e2af7ffeed1e4d2e07b502a2030eff09a06636 by benny.kra
[lld][ELF] Don't write output to the test directory. NFC.
The file was modifiedlld/test/ELF/lto/warn-backrefs.ll
Commit dd7095f52bda36e0f3cd37574a1cb97c7a46cffe by benny.kra
[clang][unittest] Don't hardcode the string "Assertion"

This depends on the libc implementation. Use the string from the
assertion message instead. Overly specific, but so is this entire test.
The file was modifiedclang/unittests/Basic/LineOffsetMappingTest.cpp
Commit b777d3049652746881b74152416e3ffb025a887c by benny.kra
[AMDGPU] Avoid unused variable warning in Release builds. NFC.

SIRegisterInfo.cpp:480:19: error: unused variable 'SOffset'
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Commit a877bda397bb0ace3688c687281dbc3e8d00204a by eleviant
Fix issue in cortex-a57 sched model

Differential revision: https://reviews.llvm.org/D90152
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
Commit 37e0fdd072a95b51bcd0eb6b08d2762aa304e766 by nicolas.vasilache
[mlir][Linalg] Add basic support for TileAndFuse on Linalg on tensors.

This revision allows the fusion of the producer of input tensors in the consumer under a tiling transformation (which produces subtensors).
Many pieces are still missing (e.g. support init_tensors, better refactor LinalgStructuredOp interface support, try to merge implementations and reuse code) but this still allows getting started.

The greedy pass itself is just for testing purposes and will be extracted in a separate test pass.

Differential revision: https://reviews.llvm.org/D89491
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h
The file was addedmlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
Commit e74f66125ebb3b43720b6803b4715c8a9c361a2f by eleviant
[ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90150
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSchedule.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
Commit 242e1e9910441ad00118e580e4cbd5743c77ea5e by zequanwu
[lldb][PDB] Add ObjectFile PDB plugin

To allow loading PDB file with `target symbols add` command.

Differential Revision: https://reviews.llvm.org/D89812
The file was modifiedlldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
The file was modifiedlldb/source/Plugins/ObjectFile/CMakeLists.txt
The file was addedlldb/source/Plugins/ObjectFile/PDB/ObjectFilePDB.h
The file was modifiedlldb/source/Plugins/SymbolFile/NativePDB/CMakeLists.txt
The file was modifiedlldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h
The file was addedlldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp
The file was addedlldb/test/Shell/ObjectFile/PDB/object.test
The file was addedlldb/source/Plugins/ObjectFile/PDB/CMakeLists.txt
The file was addedlldb/source/Plugins/ObjectFile/PDB/ObjectFilePDB.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/NativePDB/PdbIndex.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/NativePDB/PdbIndex.h
Commit 66d03af88c2e4932ae53787e07f502b90ab220cc by orlando.hyams
[DebugInfo][dexter] Add dexter tests for escaped locals

Recently there has been renewed interest in improving debug-info for variables
that (partially or otherwise) live on the stack in optimised code.

At the moment instcombine speculates that stack slots are probably going to be
promoted to registers, and prepares the debug-info accordingly. It runs a
function called LowerDbgDeclare which converts dbg.declares to a set of
dbg.values after loads, and before stores and calls. Sometimes the stack
location remains (e.g. for escaped locals). If any dbg.values become undef
where the stack location is still valid we end up unnecessarily reducing
variable location coverage due to our inability to track multiple locations
simultaneously. There is a flag to disable this feature
(-instcombine-lower-dbg-declare=0), which prevents this conversion at the cost
of sometimes providing incorrect location info in the face of DSE, DCE, GVN,
CSE etc.

This has been discussed fairly extensively on PR34136.

The idea of these tests is to provide examples of situations that we should
consider when designing a new system, to aid discussions and eventually help
evaluate the implementation.

Dexter isn't ideal for observing specific optimisation behaviour. Writing an
exaustive test suite would be difficult, and the resultant suite would be
fragile. However, I think having some concrete executable examples is useful
at least as a reference.

Differential Revision: https://reviews.llvm.org/D89543
The file was addeddebuginfo-tests/dexter-tests/memvars/ctrl-flow.c
The file was addeddebuginfo-tests/dexter-tests/memvars/inlining-dse.c
The file was addeddebuginfo-tests/dexter-tests/memvars/bitcast.c
The file was addeddebuginfo-tests/dexter-tests/memvars/loop.c
The file was addeddebuginfo-tests/dexter-tests/memvars/const-branch.c
The file was addeddebuginfo-tests/dexter-tests/memvars/ptr-to.c
The file was addeddebuginfo-tests/dexter-tests/memvars/implicit-ptr.c
The file was addeddebuginfo-tests/dexter-tests/memvars/inlining.c
The file was addeddebuginfo-tests/dexter-tests/memvars/struct-dse.c
Commit 467e5cf40f5da942419624d6a722567976b28a45 by joe.ellis
[SVE][AArch64] Fix TypeSize warning in loop vectorization legality

The warning would fire when calling isDereferenceableAndAlignedInLoop
with a scalable load. Calling isDereferenceableAndAlignedInLoop with a
scalable load would result in the use of the now deprecated implicit
cast of TypeSize to uint64_t through the overloaded operator.

This patch fixes this issue by:

- no longer considering vector loads as candidates in
  canVectorizeWithIfConvert. This doesn't make sense in the context of
  identifying scalar loads to vectorize.

- making use of getFixedSize inside isDereferenceableAndAlignedInLoop --
  this removes the dependency on the deprecated interface, and will
  trigger an assertion error if the function is ever called with a
  scalable type.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D89798
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
The file was modifiedllvm/lib/Analysis/Loads.cpp
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/sve-scalable-load-in-loop.ll
Commit 0383a1a8c230581aec4f2d9d4bfb5f5ed32d2bf5 by joe.ellis
[SVE][AArch64] Fix TypeSize warning in GEP cost analysis

The warning would fire when calling getGEPCost for analyzing the cost of
a GEP instruction. This would result in the use of the now deprecated
implicit cast of TypeSize to uint64_t through the overloaded operator.

This patch fixes the issue by using getKnownMinSize instead of the
implicit cast. This is possible because the code is already
scalable-vector aware. The semantic behaviour of the code is unchanged
by this patch.

Reviewed By: sdesmalen, fpetrogalli

Differential Revision: https://reviews.llvm.org/D89872
The file was addedllvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
Commit 0f8350559325db35e0ee3423db5d29113e4eec12 by joe.ellis
[SVE][InstCombine] Fix TypeSize warning in canReplaceGEPIdxWithZero

The warning would fire when calling canReplaceGEPIdxWithZero on a GEP
whose source element type is a scalable vector. The size of scalable
vector types is not known, so this optimization cannot be performed.

This patch fixes the issue by:

- bailing out early in this routine if the GEP instruction's source
  element type is a scalable vector.

- making use of getFixedSize -- this removes the dependency on the
  deprecated interface.

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D89968
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
The file was addedllvm/test/Transforms/InstCombine/gep-can-replace-gep-idx-with-zero-typesize.ll
Commit bf60bb26ecbf4dace2a03886180be66b3ef5608a by joe.ellis
[SVE] Fix TypeSize warning in llvm::getGEPInductionOperand

We do not need to use the implicit cast here. We can instead can rely on
a comparison between two TypeSize objects instead. This algorithm will
work fine with scalable vectors.

Reviewed By: DavidTruby

Differential Revision: https://reviews.llvm.org/D90146
The file was addedllvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
The file was modifiedllvm/lib/Analysis/VectorUtils.cpp
Commit bd07be4f3f7fc062c7c80122b8796838be91abd3 by thomasraoux
[mlir][vector] Update doc strings for insert_map/extract_map and fix insert_map semantic

Based on discourse discussion, fix the doc string and remove examples with
wrong semantic. Also fix insert_map semantic by adding missing operand for
vector we are inserting into.

Differential Revision: https://reviews.llvm.org/D89563
The file was modifiedmlir/test/Dialect/Vector/vector-distribution.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/test/lib/Transforms/TestVectorTransforms.cpp
Commit 89485efc2672f79d0acc0644830d0b9975068199 by flo
[AArch64] Extend tests for insertelement improvements.

Extends the tests added in a562dc82a8d9488d35ff535302716141bc6feaa3 to
cover more vector variants.
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
Commit 0387015d7549fc2c0cc8c45d3e78114cc4fd153f by Duncan P. N. Exon Smith
SourceManager: Return non-const references in getOrCreateContentCache and related, NFC

Update a few APIs to return non-const references instead of pointers,
and remove associated `const_cast`s and non-null assertions.

Differential Revision: https://reviews.llvm.org/D90067
The file was modifiedclang/lib/Basic/SourceManager.cpp
The file was modifiedclang/include/clang/Basic/SourceManager.h
The file was modifiedclang/lib/Serialization/ASTReader.cpp
Commit b888463f8d6b1a0b003fa329c28e7348356787b5 by Louis Dionne
[libc++abi] Make sure we can run the tests in Standalone mode

The tests would previously fail if the `python` executable wasn't found,
because we were missing the mandatory find_package.
The file was modifiedlibcxx/utils/ci/run-buildbot.sh
The file was modifiedlibcxxabi/CMakeLists.txt