Started 1 mo 18 days ago
Took 10 hr on green-dragon-06

Success Build #7523 (Nov 27, 2020 8:55:17 PM)


Git (git http://labmaster3.local/git/llvm-project.git)

  1. [Hexagon] Add HVX support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns (detail)
  2. [X86] Add AVX2/AVX512 test coverage in sat-add.ll (detail)
  3. [AllocaInst] Update `getAllocationSizeInBits` to return `TypeSize`. (detail)
  4. [libc++] Introduce an indirection to create threads in the test suite (detail)
  5. [VPlan] Use VPTransformState::set in widenGEP. (detail)
  6. TargetProcessControl.cpp - Remove warning: extra ‘;’ (detail)
  7. [AArch64] Define __ARM_FEATURE_{CRC32,ATOMICS} (detail)
  8. lld-link: Let LLD_REPRODUCE control /reproduce:, like in ld.lld (detail)
  9. [AIX][XCOFF][NFC] Change geNumberOfVRSaved function name to getNumberOfVRSaved. (detail)
  10. [libc++] Use std::move in numeric algorithms (P0616R0). (detail)
  11. [Hexagon] Improve check for HVX types (detail)
  12. [RISCV] Replace sexti32/zexti32 in isel patterns where only one part of their PatFrags can match. NFCI (detail)
  13. [RISCV][LegalizeTypes] Teach type legalizer that it can promote UMIN/UMAX using SExtPromotedInteger if that's better for the target. (detail)
  14. Revert "[BasicAA] Fix BatchAA results for phi-phi assumptions" (detail)
  15. [RISCV] Remove stale FIXMEs from a couple test cases. NFC (detail)
  16. [ValueTracking] Fix assert on shufflevector of pointers (detail)
  17. [NFC] SmallVector<char...> to SmallString<...> (detail)
  18. [RISCV] Replace getSimpleValueType() with getValueType() in DAG combines to prevent asserts with weird types. (detail)
  19. Add -fintegrated-as to clang invocation (detail)
  20. [libc++] Consistently unparenthesize `numeric_limits<T>::max`. NFCI. (detail)
  21. [libc++] Support no libc++ namespace in the iterator test. (detail)
  22. [VE] Optimize emitSPAdjustment function (detail)
  23. [libc++] s/constpexr/constexpr/ in some comments. NFC. (detail)
  24. [IRSim][IROutliner] Adding the extraction basics for the IROutliner. (detail)
  25. [gn build] Port bf899e89138 (detail)
  26. Revert "[IRSim][IROutliner] Adding the extraction basics for the IROutliner." (detail)
  27. [gn build] Port a8a43b63388 (detail)
  28. [RISCV] Add tests for existing (rotr (bswap X), (i32 16))->grevi pattern for RV32. Extend same pattern to rotl and GREVIW. (detail)

Started by upstream project clang-stage2-cmake-RgSan_relay build number 3188
originally caused by:

This run spent:

  • 59 min waiting;
  • 10 hr build duration;
  • 11 hr total from scheduled to completion.
Revision: 6ee22ca6ceb71661e8dbc296b471ace0614c07e5
  • detached
Revision: acf138fae1adab346a4c967cc0b7e9247fbc83d8
  • refs/remotes/origin/master
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 7,480.
  • Still 371 days before reaching the previous zero warnings highscore.
Test Result (no failures)