Started 1 mo 6 days ago
Took 9 hr 46 min on green-dragon-06

Success Build #7619 (Jan 22, 2021 1:35:26 AM)

Changes

Git (git http://labmaster3.local/git/llvm-project.git)

  1. Remove deprecated methods from OpState. (detail)
  2. Scalar: Don't visit constants in findInnerReductionPhi in LoopInterchange (detail)
  3. [SLP] rename reduction variable to avoid shadowing; NFC (detail)
  4. [LV][ARM] Inloop reduction cost modelling (detail)
  5. [lldb-vscode] improve modules request (detail)
  6. [libc++abi] Add an option to avoid demangling in terminate. (detail)
  7. Revert [mlir] Link mlir_runner_utils statically into cuda/rocm-runtime-wrappers (cf50f4f76456) (detail)
  8. [WebAssembly] Test that invalid symbol/relocation types generate errors (detail)
  9. Fix crash when emitting NullReturn guards for functions returning BOOL (detail)
  10. Add Python bindings for the builtin dialect (detail)
  11. [llvm-mca] Initial implementation of serialization using JSON. The views (detail)
  12. [libc++abi] Simplify scan_eh_tab (detail)
  13. [gn build] Port d38be2ba0e4e (detail)
  14. [libc] Distinguish compiler and run failures (detail)
  15. [RISCV] New vector load/store in V extension v1.0 (detail)
  16. [llvm-mca] Forgot a couple of override specifiers. (detail)
  17. [RISCV] Use v8-v23 as argument registers to conform to the proposal. (detail)
  18. [flang] Address name resolution problems (detail)
  19. [llvm-mca] Test case was missing a triple. (detail)
  20. [flang] Allow NULL() actual argument for pointer dummy (detail)
  21. [libcxx] Check return value for asprintf() (detail)
  22. [flang] Fix bogus error message with binding (detail)
  23. [NFC] [TargetRegisterInfo] add another API to get srcreg through copy. (detail)
  24. [RISCV] Add a VL output to vleff intrinsics. (detail)
  25. [llvm-mca] Addressing build failures due to missing override specifiers (detail)
  26. [mlir] Support FuncOpSignatureConversion for more FunctionLike ops. (detail)
  27. [CodeGen][ObjC] Fix broken IR generated when there is a nil receiver (detail)
  28. [AMDGPU] Test case demonstrating issues with generation of .debug_frame (detail)
  29. [PowerPC] Duplicate inherited heuristic from base scheduler (detail)
  30. [Inlining] Delete redundant optnone/alwaysinline check (detail)
  31. [RISCV] Add intrinsics for RVV 1.0 vrgatherei16 (detail)
  32. [RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0 (detail)
  33. [RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7 (detail)
  34. [AArch64][GlobalISel] Make G_USUBO legal and select it. (detail)
  35. [RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions (detail)
  36. [RISCV] Correct DWARF number for vector registers. (detail)
  37. [NewPM][opt] Run the "default" AA pipeline by default (detail)
  38. [CodeGen] Use llvm::append_range (NFC) (detail)
  39. [llvm] Don't include StringSwitch.h where unnecessary (NFC) (detail)
  40. [llvm] Use isDigit (NFC) (detail)
  41. [mlir] Enable passing crash reproducer stream factory method (detail)
  42. Revert "[NewPM][opt] Run the "default" AA pipeline by default" (detail)
  43. [AMDGPU][Inliner] Remove amdgpu-inline and add a new TTI inline hook (detail)
  44. [NFC] Disallow unused prefixes under llvm/test (detail)
  45. [ASTReader] Allow controlling separately whether validation should be disabled for a PCH vs a module file (detail)
  46. [JITLink][ELF/x86-64] Range check 32-bit relocs. (detail)
  47. [NewPM][opt] Run the "default" AA pipeline by default (detail)
  48. [test] Make incorrect-exit-count.ll work under NPM (detail)
  49. [mlir][Linalg] Introduce linalg.pad_tensor op. (detail)
  50. [mlir][StandardToSPIRV] Add support for lowering uitofp to SPIR-V (detail)
  51. [AArch64][GlobalISel] Implement widenScalar for signed overflow (detail)
  52. [TargetLowering] Simplify some code in SimplifySetCC that tries to handle SIGN_EXTEND_INREG operand types that should never happen. NFCI (detail)

Started by upstream project clang-stage2-cmake-RgSan_relay build number 3284
originally caused by:

This run spent:

  • 1 hr 0 min waiting;
  • 9 hr 46 min build duration;
  • 10 hr total from scheduled to completion.
Revision: 5660dc5968ec6dacba1917b741d660c582f69e9e
  • detached
Revision: daab19c5e8ff4b164838fceba6f96085571ba895
  • refs/remotes/origin/main
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 7,612.
  • Still 383 days before reaching the previous zero warnings highscore.
Test Result (no failures)