Started 18 days ago
Took 1 hr 21 min on green-dragon-09

Success Build #17775 (Jun 8, 2019 4:11:24 AM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 362874
  • http://llvm.org/svn/llvm-project/cfe/trunk : 362856
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 362859
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 362745
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 362866
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 362811
Changes
  1. [ARM] Adjust isLegalT1AddressImmediate for non-legal types

    Types such as float and i64's do not have legal loads in Thumb1, but will still
    be loaded with a LDR (or potentially multiple LDR's). As such we can treat the
    cost of addressing mode calculations the same as an i32 and get some optimisation
    benefits.

    Differential Revision: https://reviews.llvm.org/D62968 (detail/ViewSVN)
    by dmgreen
  2. [ARM] Add MVE addressing to isLegalT2AddressImmediate

    Now with MVE being added, we can add the vector addressing mode costs for it.
    These are generally imm7 multiplied by the size of the type being loaded /
    stored.

    Differential Revision: https://reviews.llvm.org/D62967 (detail/ViewSVN)
    by dmgreen
  3. [ARM] Add fp16 addressing to isLegalT2AddressImmediate

    The fp16 version of VLDR takes a imm8 multiplied by 2. This updates the costs
    to account for those, and adds extra testing. It is dependant upon hasFPRegs16
    as this is what the load/store instructions require.

    Differential Revision: https://reviews.llvm.org/D62966 (detail/ViewSVN)
    by dmgreen
  4. [ARM] Add extra gep costmodel tests for MVE and half float. NFC (detail/ViewSVN)
    by dmgreen
  5. [ARM] Add HasNEON for all Neon patterns in ARMInstrNEON.td. NFCI

    We are starting to add an entirely separate vector architecture to the ARM
    backend. To do that we need at least some separation between the existing NEON
    and the new MVE code. This patch just goes through the Neon patterns and
    ensures that they are predicated on HasNEON, giving MVE a stable place to start
    from.

    No tests yet as this is largely an NFC, and we don't have the other target that
    will treat any of these intructions as legal.

    Differential Revision: https://reviews.llvm.org/D62945 (detail/ViewSVN)
    by dmgreen
  6. [SystemZ]  Fix CMakeLists.txt for alphabetical order (NFC). (detail/ViewSVN)
    by jonpa
  7. [SystemZ, RegAlloc]  Favor 3-address instructions during instruction selection.

    This patch aims to reduce spilling and register moves by using the 3-address
    versions of instructions per default instead of the 2-address equivalent
    ones. It seems that both spilling and register moves are improved noticeably
    generally.

    Regalloc hints are passed to increase conversions to 2-address instructions
    which are done in SystemZShortenInst.cpp (after regalloc).

    Since the SystemZ reg/mem instructions are 2-address (dst and lhs regs are
    the same), foldMemoryOperandImpl() can no longer trivially fold a spilled
    source register since the reg/reg instruction is now 3-address. In order to
    remedy this, new 3-address pseudo memory instructions are used to perform the
    folding only when the dst and lhs virtual registers are known to be allocated
    to the same physreg. In order to not let MachineCopyPropagation run and
    change registers on these transformed instructions (making it 3-address), a
    new target pass called SystemZPostRewrite.cpp is run just after
    VirtRegRewriter, that immediately lowers the pseudo to a target instruction.

    If it would have been possibe to insert a COPY instruction and change a
    register operand (convert to 2-address) in foldMemoryOperandImpl() while
    trusting that the caller (e.g. InlineSpiller) would update/repair the
    involved LiveIntervals, the solution involving pseudo instructions would not
    have been needed. This is perhaps a potential improvement (see Phabricator
    post).

    Common code changes:

    * A new hook TargetPassConfig::addPostRewrite() is utilized to be able to run a
    target pass immediately before MachineCopyPropagation.

    * VirtRegMap is passed as an argument to foldMemoryOperand().

    Review: Ulrich Weigand, Quentin Colombet
    https://reviews.llvm.org/D60888 (detail/ViewSVN)
    by jonpa
  8. update debugging docs to be less out of date (detail/ViewSVN)
    by ericwf

Started by upstream project Clang Stage 1: cmake, RA, using system compiler build number 57344
originally caused by:

Started by upstream project Clang Stage 1: cmake, RA, using system compiler build number 57345
originally caused by:

Started by upstream project Clang Stage 1: cmake, RA, using system compiler build number 57346
originally caused by:

Started by upstream project Clang Stage 1: cmake, RA, using system compiler build number 57347
originally caused by:

Started by upstream project Clang Stage 1: cmake, RA, using system compiler build number 57348
originally caused by:

This run spent:

  • 7 hr 41 min waiting;
  • 1 hr 21 min build duration;
  • 9 hr 2 min total from scheduled to completion.
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 17,762.
  • Still 72 days before reaching the previous zero warnings highscore.