SuccessChanges

Summary

  1. [NFC] Test if commit access granted.
  2. Make test not write to source directory
  3. [X86] Use EVEX instructions for f128 FAND/FOR/FXOR when avx512vl is enabled.
  4. [X86] Convert f32/f64 FANDN/FAND/FOR/FXOR to vector logic ops and scalar_to_vector/extract_vector_elts to reduce isel patterns. Previously we did the equivalent operation in isel patterns with COPY_TO_REGCLASS operations to transition. By inserting scalar_to_vetors and extract_vector_elts before isel we can allow each piece to be selected individually and accomplish the same final result. I ideally we'd use vector operations earlier in lowering/combine, but that looks to be more difficult. The scalar-fp-to-i64.ll changes are because we have a pattern for using movlpd for store+extract_vector_elt. While an f64 store uses movsd. The encoding sizes are the same.
Revision 362917 by lkail:
[NFC] Test if commit access granted.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/PowerPC/extract-and-store.ll (diff)llvm.src/test/CodeGen/PowerPC/extract-and-store.ll
Revision 362916 by nico:
Make test not write to source directory
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The file was modified/llvm/trunk/test/tools/llvm-lib/machine-mismatch.test (diff)llvm.src/test/tools/llvm-lib/machine-mismatch.test
Revision 362915 by ctopper:
[X86] Use EVEX instructions for f128 FAND/FOR/FXOR when avx512vl is enabled.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td (diff)llvm.src/lib/Target/X86/X86InstrVecCompiler.td
Revision 362914 by ctopper:
[X86] Convert f32/f64 FANDN/FAND/FOR/FXOR to vector logic ops and scalar_to_vector/extract_vector_elts to reduce isel patterns.

Previously we did the equivalent operation in isel patterns with
COPY_TO_REGCLASS operations to transition. By inserting
scalar_to_vetors and extract_vector_elts before isel we can
allow each piece to be selected individually and accomplish the
same final result.

I ideally we'd use vector operations earlier in lowering/combine,
but that looks to be more difficult.

The scalar-fp-to-i64.ll changes are because we have a pattern for
using movlpd for store+extract_vector_elt. While an f64 store
uses movsd. The encoding sizes are the same.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (diff)llvm.src/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.td (diff)llvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.td (diff)llvm.src/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/test/CodeGen/X86/scalar-fp-to-i64.ll (diff)llvm.src/test/CodeGen/X86/scalar-fp-to-i64.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sqrt-fastmath-mir.ll (diff)llvm.src/test/CodeGen/X86/sqrt-fastmath-mir.ll