Started 13 days ago
Took 1 hr 20 min on green-dragon-08

Success Build #17918 (Jul 10, 2019 10:50:01 AM)

  • : 365672
  • : 365669
  • : 365591
  • : 364589
  • : 365562
  • : 365634
  1. [LoopRotate + MemorySSA] Keep an <instruction-cloned instruction> map.

    The map kept in loop rotate is used for instruction remapping, in order
    to simplify the clones of instructions. Thus, if an instruction can be
    simplified, its simplified value is placed in the map, even when the
    clone is added to the IR. MemorySSA in contrast needs to know about that
    clone, so it can add an access for it.
    To resolve this: keep a different map for MemorySSA.

    Reviewers: george.burgess.iv

    Subscribers: jlebar, Prazek, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by asbirlea
  2. [ORC] Add custom IR compiler configuration to LLJITBuilder to enable obj caches.

    LLJITBuilder now has a setCompileFunctionCreator method which can be used to
    construct a CompileFunction for the LLJIT instance being created. The motivating
    use-case for this is supporting ObjectCaches, which can now be set up at
    compile-function construction time. To demonstrate this an example project,
    LLJITWithObjectCache, is included. (detail/ViewSVN)
    by Lang Hames
  3. [X86] Regenerate tests. NFCI.

    Hasn't been regenerated since the update script could merge 32/64-bit checks. (detail/ViewSVN)
    by rksimon
  4. [X86] Change the IR sequence for _mm_storeh_pi and _mm_storel_pi to perform the store as a <2 x float> instead of i64.

    This is similar to what we do for loadl_pi and loadh_pi. (detail/ViewSVN)
    by ctopper
  5. [X86] Add guards to some of the x86 intrinsic tests to skip 64-bit mode only intrinsics when compiled for 32-bit mode.

    All the command lines are for 64-bit mode, but sometimes I compile
    the tests in 32-bit mode to see what assembly we get and we need
    to skip these to do that. (detail/ViewSVN)
    by ctopper
  6. [X86] Add tests for an alternative sequence for _mm_storel_pi/_mm_storeh_pi intrinsics. NFC (detail/ViewSVN)
    by ctopper
  7. [clang] Preserve names of addrspacecast'ed values.

    Differential Revision: (detail/ViewSVN)
    by vzakhari
  8. [TargetLowering] support BlockAddress as "i" inline asm constraint

    This allows passing address of labels to inline assembly "i" input

    Fixes pr/42502.

    Reviewers: ostannard

    Reviewed By: ostannard

    Subscribers: void, echristo, nathanchance, ostannard, javed.absar, hiraditya, llvm-commits, srhines

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by nickdesaulniers
  9. [NFC][InstCombine] Fixup some tests in just-added "omit mask before left-shift" tests (detail/ViewSVN)
    by lebedevri
  10. MC: AArch64: Add support for pg_hi21_nc relocation specifier.

    Differential Revision: (detail/ViewSVN)
    by pcc
  11. [CodeExtractor] Fix sinking of allocas with multiple bitcast uses (PR42451)

    An alloca which can be sunk into the extraction region may have more
    than one bitcast use. Move these uses along with the alloca to prevent

    Testing: check-llvm, stage2 build of clang


    Differential Revision: (detail/ViewSVN)
    by Vedant Kumar
  12. [CodeExtractor] Simplify findAllocas, NFC

    Split getLifetimeMarkers out into its own method and have it return a

    Differential Revision: (detail/ViewSVN)
    by Vedant Kumar
  13. GlobalISel: Legalization for G_FMINNUM/G_FMAXNUM (detail/ViewSVN)
    by arsenm
  14. GlobalISel: Define the full family of FP min/max instructions (detail/ViewSVN)
    by arsenm

Started by upstream project SVN: Clang Stage 1: cmake, RA, using system compiler build number 57860
originally caused by:

Started by upstream project SVN: Clang Stage 1: cmake, RA, using system compiler build number 57861
originally caused by:

This run spent:

  • 1 hr 12 min waiting;
  • 1 hr 20 min build duration;
  • 2 hr 33 min total from scheduled to completion.
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 17,881.
  • Still 67 days before reaching the previous zero warnings highscore.