SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [ARM] Extract from a VDUP (details)
  2. Implement _ExtInt ABI for all ABIs in Clang, enable type for ABIs (details)
  3. [VectorCombine] add tests for possible scalarization; NFC (details)
  4. [libc++] Fix broken modules tests on single-threaded systems (details)
  5. [ARM] VMOVrh of VMOVhr (details)
  6. AMDGPU: Insert kernarg code after allocas (details)
  7. [X86][SSE] combineX86ShuffleChain - remove unused shuffle(vzext_load(),undef) combine. (details)
  8. [DAGCombiner] sink target-supported FP<->int cast op after concat vectors (details)
  9. For PAL, make sure Scratch Buffer Descriptor do not clobber GIT pointer (details)
  10. [MIR] Fix a bug in MIR printer. (details)
  11. [ARM] VMOVhr load -> vldr (details)
  12. Add support for #pragma clang fp reassociate(on|off) (details)
  13. [RISCV][NFC] Add more constant materialization tests (details)
  14. [AMDGPU] Don't implement GCNHazardRecognizer::PreEmitNoops(SUnit *) (details)
  15. [AMDGPU] Drop 16 bit subreg suffixes on print (details)
Commit a349949f8ab15c50750880001b4c132aef29da25 by david.green
[ARM] Extract from a VDUP

If we get into the situation where we are extracting from a VDUP, the
extracted value is just the origin, so long as the types match or we can
bitcast between the two.

Differential Revision: https://reviews.llvm.org/D78708
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vdup.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit 8a1c999c9b0817d4de778a62965b4af86416e4b7 by erich.keane
Implement _ExtInt ABI for all ABIs in Clang, enable type for ABIs

This is the result of an audit of all of the ABIs in clang to implement
and enable the type for those targets.

Additionally, this finds an issue with integer-promotion passing for a
few platforms when using _ExtInt of < int, so this also corrects that
resulting in signext/zeroext being on a params of those types in some
platforms.

Differential Revisions: https://reviews.llvm.org/D79118
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedclang/lib/Basic/Targets/Mips.h
The file was modifiedclang/lib/Basic/Targets/SystemZ.h
The file was modifiedclang/test/CodeGenCXX/ext-int.cpp
The file was modifiedclang/lib/Basic/Targets/AArch64.h
The file was modifiedclang/lib/Basic/Targets/Hexagon.h
The file was modifiedclang/lib/Basic/Targets/Sparc.h
The file was removedclang/test/Sema/ext-int-not-supported.c
The file was modifiedclang/test/CodeGen/ext-int-sanitizer.cpp
The file was modifiedclang/lib/CodeGen/ABIInfo.h
The file was modifiedclang/lib/Basic/Targets/PNaCl.h
The file was modifiedclang/lib/Basic/Targets/Lanai.h
The file was modifiedclang/lib/Basic/Targets/PPC.h
The file was modifiedclang/lib/Basic/Targets/WebAssembly.h
The file was modifiedclang/lib/Basic/Targets/XCore.h
The file was modifiedclang/lib/Basic/Targets/RISCV.h
The file was modifiedclang/lib/Basic/Targets/AMDGPU.h
The file was modifiedclang/lib/Basic/Targets/SPIR.h
The file was modifiedclang/lib/Basic/Targets/ARM.h
The file was modifiedclang/lib/Basic/Targets/ARC.h
The file was modifiedclang/lib/Basic/Targets/NVPTX.h
The file was modifiedclang/test/CodeGen/ext-int-cc.c
Commit e3eb297deba312b7ba4a2a910714534df3e987bb by spatel
[VectorCombine] add tests for possible scalarization; NFC
The file was addedllvm/test/Transforms/VectorCombine/X86/insert-binop.ll
Commit c82f9eba4a559e23bc0c356ac8fc0c3bda2801a1 by Louis Dionne
[libc++] Fix broken modules tests on single-threaded systems

Since c0cd106fcc9f, we add __config_site macro defines to the compiler
command line whether we are building with modules or not. This means
that the modules tests are expected to fail on single-threaded systems
whether we build with modules or not.
The file was modifiedlibcxx/test/libcxx/modules/stds_include.sh.cpp
The file was modifiedlibcxx/test/libcxx/modules/stdint_h_exports.compile.pass.cpp
The file was modifiedlibcxx/test/libcxx/modules/clocale_exports.compile.pass.cpp
The file was modifiedlibcxx/test/libcxx/modules/cinttypes_exports.compile.pass.cpp
The file was modifiedlibcxx/test/libcxx/modules/inttypes_h_exports.compile.pass.cpp
The file was modifiedlibcxx/test/libcxx/modules/cstdint_exports.compile.pass.cpp
Commit d05f8a38c54a85c54b3e864a988acbe521aaa032 by david.green
[ARM] VMOVrh of VMOVhr

A VMOVhr of a VMOVrh can be simply folded to the original HPR value.

Differential Revision: https://reviews.llvm.org/D78710
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vdup.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit 074c371a4835e7821dd5c9919a9299e342c944de by Matthew.Arsenault
AMDGPU: Insert kernarg code after allocas

This produces more normal looking IR by keeping all the allocas
clustered at the start of the block.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/lower-kernargs.ll
Commit f5f7fd990e0e9c6f786d48d9a6ea832f9d706c1a by llvm-dev
[X86][SSE] combineX86ShuffleChain - remove unused shuffle(vzext_load(),undef) combine.

This should always be caught by the various VZEXT_MOVL handling in combineTargetShuffle and SimplifyDemandedVectorEltsForTargetNode.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2f1fe1864d2516f0f5d818140994caf795ccc9aa by spatel
[DAGCombiner] sink target-supported FP<->int cast op after concat vectors

Try to combine N short vector cast ops into 1 wide vector cast op:
concat (cast X), (cast Y)... -> cast (concat X, Y...)

This is part of solving PR45794:
https://bugs.llvm.org/show_bug.cgi?id=45794

As noted in the code comment, this is uglier than I was hoping because
the opcode determines whether we pass the source or destination type
to isOperationLegalOrCustom(). Also IIUC, there's no way to validate
what the other (dest or src) type is. Without the extra legality check
on that, there's an ARM regression test in:
test/CodeGen/ARM/isel-v8i32-crash.ll
...that will crash trying to lower an unsupported v8f32 to v8i16.

Differential Revision: https://reviews.llvm.org/D79360
The file was modifiedllvm/test/CodeGen/X86/concat-cast.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/avx-shift.ll
Commit f7060f4f88fb493753d1f8277f779c42e7cade2f by Matthew.Arsenault
For PAL, make sure Scratch Buffer Descriptor do not clobber GIT pointer

Since SRSRC has alignment requirements, first find non GIT pointer clobbered
registers for SRSRC and then if those registers clobber preloaded Scratch Wave
Offset register, copy the Scratch Wave Offset register to a free SGPR.
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/scratch-simple.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.h
The file was addedllvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
Commit e38018b80d8e60206268740c688236734dea7b86 by michael.hliao
[MIR] Fix a bug in MIR printer.

- Need to skip the assignment of `ID`, which is used to index that two
  object arrays.
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
Commit f5f83cf4df3e75d8b88214928af19b64849c432a by david.green
[ARM] VMOVhr load -> vldr

Much like the similar combine added recently for VMOVrh load, this
adds a fold for VMOVhr load turning it into a vldr.f16 as opposed to a
vldrh and vmov.f16.

Differential Revision: https://reviews.llvm.org/D78714
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit c355bec749e94c601a42e435f6c98b956f3965ac by melanie.blower
Add support for #pragma clang fp reassociate(on|off)

Reviewers: rjmccall, erichkeane, sepavloff

Differential Revision: https://reviews.llvm.org/D78827
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was modifiedclang/test/Parser/pragma-fp-contract.c
The file was modifiedclang/lib/Sema/SemaAttr.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticParseKinds.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/lib/Parse/ParsePragma.cpp
The file was modifiedclang/docs/LanguageExtensions.rst
The file was modifiedclang/test/Parser/pragma-fp.cpp
The file was addedclang/test/CodeGen/fp-reassoc-pragma.cpp
Commit a3e6e624c71d60509c84e13ea3ee96c0acde65c3 by luismarques
[RISCV][NFC] Add more constant materialization tests

This patch adds more constant materialization tests, focusing on cases where
we could improve our materialization instruction sequences (particularly for
RV64). Various of these cases will be improved upon in follow-up patches.

Differential Revision: https://reviews.llvm.org/D79453
The file was modifiedllvm/test/MC/RISCV/rv64i-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll
Commit 29067aac46d4f53f75c2d7e07e1afb7cb36212be by jay.foad
[AMDGPU] Don't implement GCNHazardRecognizer::PreEmitNoops(SUnit *)

When called from the post-RA scheduler, hazards have already been
handled by getHazardType returning NoopHazard, so PreEmitNoops always
returns zero. Remove it. NFC.

Historical note: PreEmitNoops was added to the hazard recognizer
interface as an optional feature to support dispatch group formation on
the POWER target:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20131202/197470.html
So it seems right that we shouldn't need to implement it.

We do still implement the other overload PreEmitNoops(MachineInstr *)
because that is used by the PostRAHazardRecognizer pass.

Differential Revision: https://reviews.llvm.org/D79476
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
Commit 54d6dfe9968da7144280130b368d386e6e24f881 by Stanislav.Mekhanoshin
[AMDGPU] Drop 16 bit subreg suffixes on print

We do not want to break asm syntax. These suffixes are
quite useful for debugging, so add an option to print
them. Right now it is NFC.

Differential Revision: https://reviews.llvm.org/D79435
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/lo16-hi16-illegal-copy.mir