SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [Analyzer][StreamChecker] Fixed compile error - NFC. (details)
  2. [WebAssembly] iterate stack in DebugFixup from the top. (details)
  3. [SVE] Ignore scalable vectors in InterleavedLoadCombinePass (details)
  4. [mlir][Vector] Make minor identity permutation map optional in transfer op printing and parsing (details)
  5. [mlir][Vector] Add an optional "masked" boolean array attribute to vector transfer operations (details)
  6. AMDGPU: Remove outdated comment (details)
  7. AMDGPU/GlobalISel: Fix splitting wide VALU, non-vector loads (details)
  8. [MLIR] [Linalg] Add option to use the partial view after promotion. (details)
  9. [mlir] Support optional attributes in assembly formats (details)
  10. [MLIR] Use `MLIR_INCLUDE_TESTS` to conditionally compile tests. (details)
  11. [Local] Do not ignore zexts in salvageDebugInfo, PR45923 (details)
  12. [lldb/Reproducers] Add skipIfReproducer to more tests (details)
  13. [llvm][NFC] Fixed non-compliant style in InlineAdvisor.h (details)
  14. [SystemZ] Don't create PERMUTE nodes with an undef operand. (details)
  15. [IR] Revert r2694 in BasicBlock::removePredecessor (details)
  16. Add verifier check that musttail and preallocated are not used together (details)
  17. [dsymutil] Make sure the --help output and man page are consistent (details)
  18. Fixed a typo in the comment for allocateBuffer() (details)
  19. [Loads] Require Align in isSafeToLoadUnconditionally() (NFC) (details)
  20. LoadStoreVectorizer: Match nested adds to prove vectorization is safe (details)
  21. AMDGPU/GlobalISel: Fix f64 G_FDIV lowering (details)
  22. [mlir][vulkan-runner] Add back accidentially removed header include (details)
  23. Revert "[CUDA][HIP] Workaround for resolving host device function against wrong-sided function" (details)
  24. AMDGPU: Fix illegally constant folding from V_MOV_B32_sdwa (details)
  25. [x86] Propagate memory operands during ISel DAG postprocessing (details)
  26. [compiler-rt][CMake] Fix PowerPC runtime build (details)
Commit 1907f28b47cfe9c951df43309d121679895b0edf by 1.int32
[Analyzer][StreamChecker] Fixed compile error - NFC.
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
Commit 10e2e7de0c0cb73a71eb0047f0a23db1f91361dc by aardappel
[WebAssembly] iterate stack in DebugFixup from the top.

Differential Revision: https://reviews.llvm.org/D80045
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyDebugFixup.cpp
Commit 364c595403c00431374dbcc965b6117e33a7f140 by david.sherwood
[SVE] Ignore scalable vectors in InterleavedLoadCombinePass

I have changed the pass so that we ignore shuffle vectors with
scalable vector types, and replaced VectorType with FixedVectorType
in the rest of the pass. I couldn't think of an easy way to test
this change, since for scalable vectors we shouldn't be using
shufflevectors for interleaving. This change fixes up some
type size assert warnings I found in the following test:

  CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll

Differential Revision: https://reviews.llvm.org/D79700
The file was modifiedllvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
Commit 36cdc17f8cfeffe7edb4486c02fc97faf73b23ac by ntv
[mlir][Vector] Make minor identity permutation map optional in transfer op printing and parsing

Summary:
This revision makes the use of vector transfer operatons more idiomatic by
allowing to omit and inferring the permutation_map.

Differential Revision: https://reviews.llvm.org/D80092
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
The file was modifiedmlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
The file was modifiedmlir/test/Dialect/Affine/SuperVectorize/vectorize_2d.mlir
The file was modifiedmlir/test/Dialect/Affine/SuperVectorize/vectorize_3d.mlir
The file was modifiedmlir/test/Dialect/Vector/vector-transforms.mlir
The file was modifiedmlir/test/Dialect/Affine/SuperVectorize/vectorize_1d.mlir
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.h
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/test/Conversion/VectorToLoops/vector-to-loops.mlir
The file was modifiedmlir/test/Conversion/AffineToStandard/lower-affine-to-vector.mlir
Commit 1870e787af961d1b409e18a18ddf297f02333a78 by ntv
[mlir][Vector] Add an optional "masked" boolean array attribute to vector transfer operations

Summary:
Vector transfer ops semantic is extended to allow specifying a per-dimension `masked`
attribute. When the attribute is false on a particular dimension, lowering to LLVM emits
unmasked load and store operations.

Differential Revision: https://reviews.llvm.org/D80098
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
The file was modifiedmlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
The file was modifiedmlir/test/Conversion/VectorToLoops/vector-to-loops.mlir
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Commit 681a161ff5419404ac1b3221e9a01ade25802998 by Matthew.Arsenault
AMDGPU: Remove outdated comment
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 4c70074e54348d8fb77f14583c6172e4377dc95e by Matthew.Arsenault
AMDGPU/GlobalISel: Fix splitting wide VALU, non-vector loads
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
Commit d1866f89472787dfac92a689700c4c4335a6add3 by zinenko
[MLIR] [Linalg] Add option to use the partial view after promotion.

For now the promoted buffer is indexed using the `full view`. The full view might be
slightly bigger than the partial view (which is accounting for boundaries).
Unfortunately this does not compose easily with other transformations when multiple buffers
with shapes related to each other are involved.
Take `linalg.matmul A B C` (with A of size MxK, B of size KxN and C of size MxN) and suppose we are:
- Tiling over M by 100
- Promoting A only

This is producing a `linalg.matmul promoted_A B subview_C` where `promoted_A` is a promoted buffer
of `A` of size (100xK) and `subview_C` is a subview of size mxK where m could be smaller than 100 due
to boundaries thus leading to a possible incorrect behavior.

We propose to:
- Add a new parameter to the tiling promotion allowing to enable the use of the full tile buffer.
- By default all promoted buffers will be indexed by the partial view.

Note that this could be considered as a breaking change in comparison to the way the tiling promotion
was working.

Differential Revision: https://reviews.llvm.org/D79927
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/include/mlir/Dialect/Vector/EDSC/Intrinsics.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
The file was modifiedmlir/test/lib/Transforms/TestLinalgTransforms.cpp
The file was modifiedmlir/test/Dialect/Linalg/promote.mlir
Commit a4cb9bec1ca32cc1cfc25b32c05494c200793264 by jean-michel.gorius
[mlir] Support optional attributes in assembly formats

Summary: This revision adds support for assembly formats with optional attributes. It elides optional attributes that are part of the syntax from the attribute dictionary.

Reviewers: ftynse, Kayjukh

Reviewed By: ftynse, Kayjukh

Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, jurahul, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80113
The file was modifiedmlir/test/mlir-tblgen/op-format.mlir
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
Commit 23dc948d362018a8257d8288fe9beb0d27fc9b35 by zinenko
[MLIR] Use `MLIR_INCLUDE_TESTS` to conditionally compile tests.

This is equivalent to what is done for other projects (e.g. clang).

Differential Revision: https://reviews.llvm.org/D80022
The file was modifiedmlir/CMakeLists.txt
The file was modifiedmlir/tools/mlir-opt/CMakeLists.txt
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp
Commit 623b2542446a1873fb7ea3904c4fb50e2e77fe41 by Vedant Kumar
[Local] Do not ignore zexts in salvageDebugInfo, PR45923

Summary:
When salvaging a dead zext instruction, append a convert operation to
the DIExpressions of the debug uses of the instruction, to prevent the
salvaged value from being sign-extended.

I confirmed that lldb prints out the correct unsigned result for "f" in
the example from PR45923 with this changed applied.

rdar://63246143

Reviewers: aprantl, jmorse, chrisjackson, davide

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80034
The file was modifiedllvm/test/Transforms/InstCombine/cast-mul-select.ll
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 2084330e41d301cf9eaa3495d8968bff70846c7b by Jonas Devlieghere
[lldb/Reproducers] Add skipIfReproducer to more tests

Mark more tests as unsupported with reproducers.
The file was modifiedlldb/test/API/functionalities/postmortem/netbsd-core/TestNetBSDCore.py
The file was modifiedlldb/test/API/functionalities/deleted-executable/TestDeletedExecutable.py
The file was modifiedlldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
The file was modifiedlldb/test/API/functionalities/breakpoint/step_over_breakpoint/TestStepOverBreakpoint.py
The file was modifiedlldb/test/API/functionalities/load_unload/TestLoadUnload.py
Commit 691980ebb47127c611be6e85f27e1778d5d213d8 by mtrofin
[llvm][NFC] Fixed non-compliant style in InlineAdvisor.h

Changed OnPass{Entry|Exit} -> onPass{Entry|Exit}

Also fixed a small typo in a comment.
The file was modifiedllvm/include/llvm/Analysis/InlineAdvisor.h
The file was modifiedllvm/lib/Transforms/IPO/Inliner.cpp
Commit 31ecef76275158c87d63772a70fbc282d025e7ab by paulsson
[SystemZ] Don't create PERMUTE nodes with an undef operand.

It's better to reuse the first source value than to use an undef second
operand, because that will make more resulting VPERMs have identical operands
and therefore MachineCSE more successful.

Review: Ulrich Weigand
The file was addedllvm/test/CodeGen/SystemZ/vec-perm-14.ll
The file was modifiedllvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Commit bdd8c111fc0d880eec57db860249f1707eed6982 by jay.foad
[IR] Revert r2694 in BasicBlock::removePredecessor

r2694 fixed a bug where removePredecessor could create IR with a use not
dominated by its def in a self loop. But this could only happen in an
unreachable loop, and since that time the rules have been relaxed so
that defs don't have to dominate uses in unreachable code, so the fix is
unnecessary. The regression test added in r2691 still stands.

Differential Revision: https://reviews.llvm.org/D80128
The file was modifiedllvm/lib/IR/BasicBlock.cpp
Commit a7cc275e7e8ac21ddf1b6d74e3de013d9f88d016 by aeubanks
Add verifier check that musttail and preallocated are not used together

Summary:
Currently they are not supported together. Supporting them will require
a LangRef change. See discussion in https://reviews.llvm.org/D77689.

Reviewers: rnk, efriedma

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80132
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/test/Verifier/preallocated-invalid.ll
Commit b7924d6525be103b6ffd93c7b9787d4339b3ad61 by Jonas Devlieghere
[dsymutil] Make sure the --help output and man page are consistent

As suggested by Adrian in D79398.
The file was modifiedllvm/test/tools/dsymutil/cmdline.test
The file was modifiedllvm/docs/CommandGuide/dsymutil.rst
The file was modifiedllvm/tools/dsymutil/Options.td
Commit 3c4ef745557506a51c5fc6db3d1cabeb8a133923 by antiagainst
Fixed a typo in the comment for allocateBuffer()

Differential Revision: https://reviews.llvm.org/D80087
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
Commit 736db2f710367946452f3f705010ada4227352b0 by nikita.ppv
[Loads] Require Align in isSafeToLoadUnconditionally() (NFC)

Now that load/store have required alignment, accept Align here.
This also avoids uses of getPointerElementType(), which is
incompatible with opaque pointers.
The file was modifiedllvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
The file was modifiedllvm/lib/Analysis/Loads.cpp
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp
The file was modifiedllvm/include/llvm/Analysis/Loads.h
Commit 63081dc6f642a6be61b3ef213f5c6e257f35671c by vkeles
LoadStoreVectorizer: Match nested adds to prove vectorization is safe

If both OpA and OpB is an add with NSW/NUW and with the same LHS operand,
we can guarantee that the transformation is safe if we can prove that OpA
won't overflow when IdxDiff added to the RHS of OpA.

Review: https://reviews.llvm.org/D79817
The file was modifiedllvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
The file was addedllvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll
Commit bf527a1dc410eddf5b2e176b9092bfb1de75df0e by Matthew.Arsenault
AMDGPU/GlobalISel: Fix f64 G_FDIV lowering

This was using an integer multiply instead of FP.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 715b7d8aa5d7bbddd899510cff88fb042a47d650 by antiagainst
[mlir][vulkan-runner] Add back accidentially removed header include

Differential Revision: https://reviews.llvm.org/D80149
The file was modifiedmlir/tools/mlir-vulkan-runner/CMakeLists.txt
Commit ef649e8fd5d1748764a9afca3ce0b80113a6a239 by tra
Revert "[CUDA][HIP] Workaround for resolving host device function against wrong-sided function"

Still breaks CUDA compilation.

This reverts commit e03394c6a6ff5832aa43259d4b8345f40ca6a22c.
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaCUDA.cpp
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/test/SemaCUDA/function-overload.cu
Commit b27a538dda4caf2752ed8c6c731361ddf9458b87 by Matthew.Arsenault
AMDGPU: Fix illegally constant folding from V_MOV_B32_sdwa

This was assumed to be a simple move, and interpreting the immediate
modifier operand as a materialized immediate. Apparently the SDWA pass
never produces these, but GlobalISel does emit these for some vector
shuffles.
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
Commit cd12e79e6ddd235739716fff5c6a748915f664b9 by jean-michel.gorius
[x86] Propagate memory operands during ISel DAG postprocessing

Summary:
Propagate memory operands when folding test instructions.

This was split from D80062.

Reviewers: craig.topper, rnk, lebedev.ri

Reviewed By: craig.topper

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80140
The file was addedllvm/test/CodeGen/X86/isel-postprocessing-test-fold-memop.ll
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 3f5f8f39734e88c797b003d4a0002b2eaef1ac17 by Jinsong Ji
[compiler-rt][CMake] Fix PowerPC runtime build

When build in runtime bulid mode with LLVM_ENABLE_RUNTIMES,
the base-config-ix.cmake will complain about two errors.

One is empty string in replace, the other one is unknown `TEST_BIG_ENDIAN ` command.

This patch fix it so that we can test runtime build.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D80040
The file was modifiedcompiler-rt/cmake/base-config-ix.cmake