SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [PhaseOrdering] regenerate test checks; NFC (details)
  2. AMDGPU/GlobalISel: Fix masked control flow with fallthrough blocks (details)
  3. [NFC][AIX] Remove spaces after the comma for '.csect' directive (details)
  4. [SCEV] Constant fold MultExpr before applying depth limit. (details)
  5. [InstCombine] add tests for adds with common operand; NFC (details)
  6. [InstCombine] (A + B) + B --> A + (B << 1) (details)
Commit 5a230a19ad0fa52bd7aa2169b2f0abc6b2bc47df by spatel
[PhaseOrdering] regenerate test checks; NFC

Remove some redundant/unnecessary bits too.
The file was modifiedllvm/test/Transforms/PhaseOrdering/reassociate-after-unroll.ll
Commit 66fe60220ca2b1932e06093294c72b246be54ec8 by Matthew.Arsenault
AMDGPU/GlobalISel: Fix masked control flow with fallthrough blocks

Unlike SelectionDAGBuilder, IRTranslator omits the unconditional
branch in fallthrough cases. Confusingly, the control flow pseudos
function in the opposite way the intrinsics are used, and the branch
targets always need to be swapped. We're inverting the target blocks,
so we need to figure out the old fallthrough block and insert a branch
to the original unconditional branch target.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
Commit 2419dce5d1c6338012002a9358c7c8fc6a7baca5 by xiangling_liao
[NFC][AIX] Remove spaces after the comma for '.csect' directive

To be consistent with other directives like '.comm', '.lcomm', we remove
the spaces after the comma for '.csect' on AIX.

Differential Revision: https://reviews.llvm.org/D80247
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-readonly-with-relocation.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
The file was modifiedllvm/test/CodeGen/PowerPC/test_func_desc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-func-align.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-lower-comm.ll
The file was modifiedllvm/lib/MC/MCSectionXCOFF.cpp
Commit 5451289abafd8879adf892ede7660ce8c46c6a6f by dantrushin
[SCEV] Constant fold MultExpr before applying depth limit.

Summary:
Users of SCEV reasonably assume that multiplication of two constant
SCEVs will in turn be constant.
However, that is not always the case:
First, we can get here with reached depth limit, and will create
MultExpr SCEV `C1 * C2` and cache it.
Then, we can get here with the same operands, but with small depth
level. But this time we will find existing MultExpr SCEV and return
it, instead of expected constant SCEV.

This patch changes getMultExpr to not apply depth limit to all constant
operands expression, allowing them to be folded.

Reviewers: reames, mkazantsev

Subscribers: hiraditya, javed.absar, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79893
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was addedllvm/test/Analysis/ScalarEvolution/depth-limit-overrun.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/limit-depth.ll
Commit b603794061f651695b155a0456a701d0ad82e8f4 by spatel
[InstCombine] add tests for adds with common operand; NFC
The file was modifiedllvm/test/Transforms/InstCombine/add.ll
Commit 2f7c24fe303f09308f1032515379f0abf20c5f90 by spatel
[InstCombine] (A + B) + B --> A + (B << 1)

This eliminates a use of 'B', so it can enable follow-on transforms
as well as improve analysis/codegen.

The PhaseOrdering test was added for D61726, and that shows
the limits of instcombine vs. real reassociation. We would
need to run some form of CSE to collapse that further.

The intermediate variable naming here is intentional because
there's a test at llvm/test/Bitcode/value-with-long-name.ll
that would break with the usual nameless value. I'm not sure
how to improve that test to be more robust.

The naming may also be helpful to debug regressions if this
change exposes weaknesses in the reassociation pass for example.
The file was modifiedllvm/test/Transforms/PhaseOrdering/reassociate-after-unroll.ll
The file was modifiedllvm/test/Transforms/InstCombine/add.ll
The file was modifiedllvm/test/Transforms/PGOProfile/chr.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp