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Summary

  1. [PowerPC] Pre-commit more tests for `select` codegen. NFC. (details)
  2. [GlobalISel][TableGen] Fix seg fault for zero instruction (details)
  3. [AArch64][GlobalISel] Make <2 x p0> of G_SHUFFLE_VECTOR legal. (details)
  4. [AArch64][GlobalISel] Add pre-isel lowering to convert p0 G_DUPs to use s64. (details)
Commit da3bc99bdd778ce2c22f17cab2b94eefcc285953 by lkail
[PowerPC] Pre-commit more tests for `select` codegen. NFC.
The file was modifiedllvm/test/CodeGen/PowerPC/select.ll
Commit 5e9e335a247040a175855f99dbab5957064434ba by mikael.holmen
[GlobalISel][TableGen] Fix seg fault for zero instruction

Tablegen seg faulted when parsing a Pat where the destination part has
no output (zero instruction), due to a register class lookup using
nullptr.

Reviewed By: Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D90829
The file was addedllvm/test/TableGen/GlobalISelEmitter-zero-instr.td
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
Commit 0fb76b9035c8af48f63d965faadfb4b0e58b0a4f by Amara Emerson
[AArch64][GlobalISel] Make <2 x p0> of G_SHUFFLE_VECTOR legal.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit ca7fdf7ce098ace9ba24a94e985b24cd6801240d by Amara Emerson
[AArch64][GlobalISel] Add pre-isel lowering to convert p0 G_DUPs to use s64.

This uses the same reasoning as other similar conversions just before selection,
without it we miss out on selection because the importer considers s64 and p0
distinct types.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir