Started 3 mo 29 days ago
Took 18 hr on green-dragon-09

Failed Build #4035 (May 25, 2019 3:37:10 AM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 361694
  • http://llvm.org/svn/llvm-project/cfe/trunk : 361686
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 361579
  • http://llvm.org/svn/llvm-project/lld/trunk : 361678
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 346271
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 361594
  • http://llvm.org/svn/llvm-project/test-suite/trunk : 358206
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 361687
  • http://llvm.org/svn/llvm-project/polly/trunk : 361290
Changes
  1. [CVP] Add tests for saturating add/sub ranges; NFC (detail/ViewSVN)
    by nikic
  2. [LVI][CVP] Calculate with.overflow result range

    In LVI, calculate the range of extractvalue(op.with.overflow(%x, %y), 0)
    as the range of op(%x, %y). This is mainly useful in conjunction with
    D60650: If the result of the operation is extracted in a branch guarded
    against overflow, then the value of %x will be appropriately constrained
    and the result range of the operation will be calculated taking that
    into account.

    Differential Revision: https://reviews.llvm.org/D60656 (detail/ViewSVN)
    by nikic
  3. [LVI] Extract helper for binary range calculations; NFC (detail/ViewSVN)
    by nikic
  4. [X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.

    INC/DEC is really a special case of a more generic issue. We should also turn leas into add reg/reg or add reg/imm regardless of the slow lea flags.

    This also supports LEA64_32 which has 64 bit input registers and 32 bit output registers. So we need to convert the 64 bit inputs to their 32 bit equivalents to check if they are equal to base reg.

    One thing to note, the original code preserved the kill flags by adding operands to the new instruction instead of using addReg. But I think tied operands aren't supposed to have the kill flag set. I dropped the kill flags, but I could probably try to preserve it in the add reg/reg case if we think its important. Not sure which operand its supposed to go on for the LEA64_32r instruction due to the super reg implicit uses. Though I'm also not sure those are needed since they were probably just created by an INSERT_SUBREG from a 32-bit input.

    Differential Revision: https://reviews.llvm.org/D61472 (detail/ViewSVN)
    by ctopper
  5. [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models. Add 256-bit fp xor to sandybridge zero idioms

    This copies the Sandy Bridge zero idiom support to later CPUs. Adding the AVX2 and AVX512F/VL instructions as appropriate.

    Differential Revision: https://reviews.llvm.org/D62360 (detail/ViewSVN)
    by ctopper
  6. [X86][llvm-mca] Add zero idiom tests for Intel CPUs. NFC

    This pre-commits tests for D62360 (detail/ViewSVN)
    by ctopper

Started by upstream project SVN: Clang Stage 1: cmake, RA, using system compiler build number 56851
originally caused by:

Started by upstream project SVN: Clang Stage 1: cmake, RA, using system compiler build number 56852
originally caused by:

Started by upstream project SVN: Clang Stage 1: cmake, RA, using system compiler build number 56853
originally caused by:

This run spent:

  • 7 hr 26 min waiting;
  • 18 hr build duration;
  • 1 day 1 hr total from scheduled to completion.

Identified problems

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 1

Ninja target failed

Below is a link to the first failed ninja target.
Indication 2

Compile Error

This build failed because of a compile error. Below is a list of all errors in the build log:
Indication 3