Started 2 mo 15 days ago
Took 16 hr on green-dragon-08

Failed Build #5361 (Jun 9, 2019 9:56:20 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 362920
  • http://llvm.org/svn/llvm-project/cfe/trunk : 362887
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 362859
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 362745
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 362866
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 362811
Changes
  1. [X86] When promoting i16 compare with immediate to i32, try to use sign_extend for eq/ne if the input is truncated from a type with enough sign its.

    Summary:
    Our default behavior is to use sign_extend for signed comparisons and zero_extend for everything else. But for equality we have the freedom to use either extension. If we can prove the input has been truncated from something with enough sign bits, we can use sign_extend instead and let DAG combine optimize it out. A similar rule is used by type legalization in LegalizeIntegerTypes.

    This gets rid of the movzx in PR42189. The immediate will still take 4 bytes instead of the 2 bytes plus 0x66 prefix a cmp di, 32767 would get, but it avoids a length changing prefix.

    Reviewers: RKSimon, spatel, xbolva00

    Reviewed By: xbolva00

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D63032 (detail/ViewSVN)
    by ctopper
  2. [X86] Disable f32->f64 extload when sse2 is enabled

    Summary:
    We can only use the memory form of cvtss2sd under optsize due to a partial register update. So previously we were emitting 2 instructions for extload when optimizing for speed. Also due to a late optimization in preprocessiseldag we had to handle (fpextend (loadf32)) under optsize.

    This patch forces extload to expand so that it will always be in the (fpextend (loadf32)) form during isel. And when optimizing for speed we can just let each of those pieces select an instruction independently.

    Reviewers: spatel, RKSimon

    Reviewed By: RKSimon

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D62710 (detail/ViewSVN)
    by ctopper
  3. Do not derive no-recurse attribute if function does not have exact definition.
    This is fix for https://bugs.llvm.org/show_bug.cgi?id=41336

    Reviewers: jdoerfert
    Reviewed by: jdoerfert

    Differential Revision: https://reviews.llvm.org/D63045 (detail/ViewSVN)
    by vivekvpandya
  4. [NFC] Test if commit access granted. (detail/ViewSVN)
    by lkail
  5. Make test not write to source directory (detail/ViewSVN)
    by nico
  6. [X86] Use EVEX instructions for f128 FAND/FOR/FXOR when avx512vl is enabled. (detail/ViewSVN)
    by ctopper
  7. [X86] Convert f32/f64 FANDN/FAND/FOR/FXOR to vector logic ops and scalar_to_vector/extract_vector_elts to reduce isel patterns.

    Previously we did the equivalent operation in isel patterns with
    COPY_TO_REGCLASS operations to transition. By inserting
    scalar_to_vetors and extract_vector_elts before isel we can
    allow each piece to be selected individually and accomplish the
    same final result.

    I ideally we'd use vector operations earlier in lowering/combine,
    but that looks to be more difficult.

    The scalar-fp-to-i64.ll changes are because we have a pattern for
    using movlpd for store+extract_vector_elt. While an f64 store
    uses movsd. The encoding sizes are the same. (detail/ViewSVN)
    by ctopper
  8. Revert r361953 "[SVE][IR] Scalable Vector IR Type"

    This reverts commit f4fc01f8dd3a5dfd2060d1ad0df6b90e8351ddf7.
    It caused a 3-4x slowdown when doing thinlto links, PR42210. (detail/ViewSVN)
    by nico
  9. [TargetLowering] Simplify (ctpop x) == 1

    Reviewers: craig.topper, spatel, RKSimon, bkramer

    Reviewed By: spatel

    Subscribers: javed.absar, lebedev.ri, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D63004 (detail/ViewSVN)
    by xbolva00
  10. [InstCombine] foldICmpWithLowBitMaskedVal(): 'icmp sgt/sle': avoid miscompiles

    A precondition 'x != 0' was forgotten by me:
    https://rise4fun.com/Alive/JFNP
    https://rise4fun.com/Alive/jHvL

    These 4 folds with non-constants could be re-enabled,
    but for now let's go for the simplest solution.

    https://bugs.llvm.org/show_bug.cgi?id=42198 (detail/ViewSVN)
    by lebedevri
  11. [NFC][InstCombine] Revisit canonicalize-constant-low-bit-mask-and-icmp-s* tests in preparatio for PR42198.

    The `icmp sgt`/`icmp sle` variants are, too, miscompiles:
    https://rise4fun.com/Alive/JFNP
    https://rise4fun.com/Alive/jHvL
    A precondition 'x != 0' was forgotten by me.

    While ensuring test coverage for `-1`, also add test coverage
    for `0` mask. Mask `0` is allowed for all the folds,
    mask `-1` is allowed for all the folds with unsigned `icmp` pred.
    Constant mask `0` is missed though.

    https://bugs.llvm.org/show_bug.cgi?id=42198 (detail/ViewSVN)
    by lebedevri
  12. [InstCombine] change canonicalization to fabs() to use FMF on fneg

    This isn't the ideal fix (use FMF on the select), but it's still an
    improvement until we have better FMF propagation to selects and other
    FP math operators.

    I don't think there's much risk of regression from this change by
    not including the FMF on the fcmp any more. The nsz/nnan FMF
    should be the same on the fcmp and the fneg (fsub) because they
    have the same operand.

    This works around the most glaring FMF logical inconsistency cited
    in PR38086:
    https://bugs.llvm.org/show_bug.cgi?id=38086 (detail/ViewSVN)
    by spatel
  13. [NFC] Adjust test for D63004 (detail/ViewSVN)
    by xbolva00
  14. [NFC] Added test from PR19758 (detail/ViewSVN)
    by xbolva00
  15. [NFC] Added test from PR42084 for D63058 (detail/ViewSVN)
    by xbolva00
  16. [InstCombine] Add tests for usub.sat(x,y)+y etc; NFC

    For PR42178. (detail/ViewSVN)
    by nikic
  17. [InstSimplify] reduce code duplication for fcmp folds; NFC (detail/ViewSVN)
    by spatel
  18. [InstSimplify] enhance fcmp fold with never-nan operand

    This is another step towards correcting our usage of fast-math-flags when applied on an fcmp.
    In this case, we are checking for 'nnan' on the fcmp itself rather than the operand of
    the fcmp. But I'm leaving that clause in until we're more confident that we can stop
    relying on fcmp's FMF.

    By using the more general "isKnownNeverNaN()", we gain a simplification shown on the
    tests with 'uitofp' regardless of the FMF on the fcmp (uitofp never produces a NaN).
    On the tests with 'fabs', we are now relying on the FMF for the call fabs instruction
    in addition to the FMF on the fcmp.

    This is a continuation of D62979 / rL362879. (detail/ViewSVN)
    by spatel
  19. [InstSimplify] add tests for fcmp with known-never-nan operands; NFC

    Opposite predicate for rL362742 / rL362879 / D62979 (detail/ViewSVN)
    by spatel
  20. [MIR] Add simple PRE pass to MachineCSE

    This is the second part of the commit fixing PR38917 (hoisting
    partitially redundant machine instruction). Most of PRE (partitial
    redundancy elimination) and CSE work is done on LLVM IR, but some of
    redundancy arises during DAG legalization. Machine CSE is not enough
    to deal with it. This simple PRE implementation works a little bit
    intricately: it passes before CSE, looking for partitial redundancy
    and transforming it to fully redundancy, anticipating that the next
    CSE step will eliminate this created redundancy. If CSE doesn't
    eliminate this, than created instruction will remain dead and eliminated
    later by Remove Dead Machine Instructions pass.

    The third part of the commit is supposed to refactor MachineCSE,
    to make it more clear and to merge MachinePRE with MachineCSE,
    so one need no rely on further Remove Dead pass to clear instrs
    not eliminated by CSE.

    First step: https://reviews.llvm.org/D54839

    Fixes llvm.org/PR38917

    This is fixed recommit of r361356 after PowerPC64 multistage build failure. (detail/ViewSVN)
    by anton-afanasyev

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17785
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17786
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17787
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17788
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17789
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17790
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17791
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17792
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17793
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17794
originally caused by:

This run spent:

  • 17 hr waiting;
  • 16 hr build duration;
  • 1 day 9 hr total from scheduled to completion.

Identified problems

Compile Error

This build failed because of a compile error. Below is a list of all errors in the build log:
Indication 1

Missing test results

The test result file Jenkins is looking for does not exist after the build.
Indication 2

Ninja target failed

Below is a link to the first failed ninja target.
Indication 3

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 4