Started 4 mo 29 days ago
Took 17 hr on green-dragon-09

Failed Build #5369 (Jun 24, 2019 5:13:27 PM)

  • : 364255
  • : 364251
  • : 364231
  • : 363952
  • : 364241
  • : 364222
  1. [InstCombine] Fold  icmp eq/ne (and %x, C), 0 iff (-C) is power of two -> %x u</u>= (-C)  earlier.

    To generate simplified IR, make sure fold
      (X & ~C) ==/!= 0 --> X u</u>= C+1

    is scheduled before fold
      ((X << Y) & C) == 0 -> (X & (C >> Y)) == 0.

    Reviewers: lebedev.ri, efriedma, spatel, craig.topper

    Reviewed By: lebedev.ri

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by huihuiz
  2. [llvm-objcopy][NFC] Refactor output target parsing

    Use an enum instead of string to hold the output file format in Config.InputFormat and Config.OutputFormat. It's essential to support other output file formats other than ELF.

    Reviewers: espindola, alexshap, rupprecht, jhenderson

    Reviewed By: rupprecht, jhenderson

    Subscribers: jyknight, compnerd, emaste, arichardson, fedor.sergeev, jakehehrlich, MaskRay, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by seiya
  3. DataExtractor: use decodeSLEB128 to implement getSLEB128

    Should've been NFC, but turns out DataExtractor had better test coverage
    for decoding SLEB128 than the decodeSLEB128 did - revealing a couple of
    bugs (one in the error handling, another in sign extension). So fixed
    those to get the DataExtractor tests passing again. (detail/ViewSVN)
    by dblaikie
  4. [llvm-objcopy][MachO] Fix strict-aliasing warning. NFCI

    Use MachOObjectFile::isRelocationScattered instead of reinterpret_cast.


    Reviewers: alexshap, rupprecht, jhenderson

    Reviewed By: alexshap

    Subscribers: dendibakh, bjope, uabelho, jakehehrlich, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by seiya
  5. AMDGPU: Fix missing declaration for mbcnt builtins (detail/ViewSVN)
    by arsenm
  6. Revert "[NVPTX][NFC] Fix documentation for shfl instructions." The
    original documentation is correct as it matches the C++ builtins. (detail/ViewSVN)
    by timshen
  7. [NFC] Fix tests added in r364225 which failed on Windows due to incorrect path separators. (detail/ViewSVN)
    by dyung
  8. [NVPTX][NFC] Fix documentation for shfl instructions. (detail/ViewSVN)
    by timshen
  9. [NFC] Add missing consts into memoryaccess_def_iterator (detail/ViewSVN)
    by Vitaly Buka
  10. [InstCombine] squash is-not-power-of-2 using ctpop

    This is the Demorgan'd 'not' of the pattern handled in:
    D63660 / rL364153

    This is another intermediate IR step towards solving PR42314:

    We can test if a value is not a power-of-2 using ctpop(X) > 1,
    so combining that with an is-zero check of the input is the
    same as testing if not exactly 1 bit is set:

    (X == 0) || (ctpop(X) u> 1) --> ctpop(X) != 1 (detail/ViewSVN)
    by spatel
  11. Fix test cl-response-file.c to work on all platforms including Windows/Solaris.

    Differential Revision: (detail/ViewSVN)
    by dyung
  12. AMDGPU/GlobalISel: Add tests for regbankselect of v2s16 and/or/xor (detail/ViewSVN)
    by arsenm
  13. Fix test failures due to modified wording in Clang diagnostics. (detail/ViewSVN)
    by rsmith
  14. Fix test failures when using a custom ABI namespace. (detail/ViewSVN)
    by rsmith
  15. [SLP] NFC: Fixed typo in comment (detail/ViewSVN)
    by vporpo
  16. [Syntax] Do not glue multiple empty PP expansions to a single mapping

    This change makes sure we have a single mapping for each macro expansion,
    even if the result of expansion was empty.

    To achieve that, we take information from PPCallbacks::MacroExpands into
    account. Previously we relied only on source locations of expanded tokens.

    Reviewers: sammccall

    Reviewed By: sammccall

    Subscribers: cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by ibiryukov
  17. InstCombine: Preserve nuw when reassociating nuw ops [3/3]

    Alive says this is OK. (detail/ViewSVN)
    by arsenm
  18. InstCombine: Preserve nuw when reassociating nuw ops [2/3]

    Alive says this is OK. (detail/ViewSVN)
    by arsenm
  19. InstCombine: Preserve nuw when reassociating nuw ops [1/3]

    Alive says this is OK. (detail/ViewSVN)
    by arsenm
  20. [NFC][Reassociate] Add unary FNeg tests to fast-ReassociateVector.ll (detail/ViewSVN)
    by mcinally
  21. (Reland with changes) Adding a function for setting coverage output file.

    User code can open a file on its own and pass it to the runtime, rather than
    specifying a name and having the runtime open the file. This supports the use
    case where a process cannot open a file on its own but can receive a file
    descriptor from another process.

    Relanding The original revision unlocked
    the file before calling flush, this revision fixes that.

    Reviewers: Dor1s, davidxl

    Reviewed By: Dor1s

    Subscribers: #sanitizers, llvm-commits

    Tags: #sanitizers, #llvm

    Differential Revision: (detail/ViewSVN)
    by sajjadm
  22. NFC: DataExtractor: use decodeULEB128 to implement getULEB128 (detail/ViewSVN)
    by dblaikie
  23. [CVP] Reenable nowrap flag inference

    Inference of nowrap flags in CVP has been disabled, because it
    triggered a bug in LFTR (
    This issue has been fixed in D60935, so we should be able to reenable
    nowrap flag inference now.

    Differential Revision: (detail/ViewSVN)
    by nikic
  24. [InstCombine] add tests for more variants of isPowerOf2; NFC (detail/ViewSVN)
    by spatel
  25. Augment location information when dumping the AST to JSON.

    Rather than create JSON objects for source locations and ranges, we instead stream them out directly. This allows us to elide duplicate information (without JSON field reordering causing an issue) like file names and line numbers, similar to the text dump. This also adds token length information when dumping the source location. (detail/ViewSVN)
    by aaronballman
  26. llvm-symbolizer: Add a FRAME command.

    This command prints a description of the referenced function's stack frame.
    For each formal parameter and local variable, the tool prints:

    - function name
    - variable name
    - file/line of declaration
    - FP-relative variable location (if available)
    - size in bytes
    - HWASAN tag offset

    This information will be used by the HWASAN runtime to identify local
    variables in UAR reports.

    Differential Revision: (detail/ViewSVN)
    by pcc
  27. [InstCombine] Regenerate test pr17827. NFCI.

    Prep work for upcoming patch D63505. (detail/ViewSVN)
    by huihuiz
  28. [clang-doc] Add basic support for templates and typedef

    In serialize::parseBases(...), when a base record is a template
    specialization, the specialization was used as the parent. It should be
    the base template so there is only one file generated for this record.
    When the specialized template is implicitly declared the reference USR
    corresponded to the GlobalNamespace's USR, this will now be the base
    template's USR.

    More information about templates will be added later.

    In serialize::emiInfo(RecorDecl*, ...), typedef records were not handled
    and the name was empty. This is now handled and a IsTypeDef attribute is
    added to RecordInfo struct.

    In serialize::emitInfo(CXXMethodDecl*, ...), template specialization is
    handled like in serialize::parseBases(...).

    Bitcode writer and reader are modified to handle the new attribute of

    Submitted on behalf of Diego Astiazarán (
    Differential Revision: (detail/ViewSVN)
    by juliehockett
  29. [CodeGen] Add missing vector type legalization for ctlz_zero_undef

    Widen vector result type for ctlz_zero_undef and cttz_zero_undef the same as
    ctlz and cttz.

    Differential Revision: (detail/ViewSVN)
    by froese
  30. [Tests] Add cases where we're failing to discharge provably loop exits (tests for D63733) (detail/ViewSVN)
    by reames
  31. [SLP] Support unary FNeg vectorization

    Differential Revision: (detail/ViewSVN)
    by mcinally
  32. Remove flag for no longer supported MSVC version (detail/ViewSVN)
    by nico
  33. AMDGPU/GlobalISel: Select G_TRUNC (detail/ViewSVN)
    by arsenm
  34. AMDGPU/GlobalISel: RegBankSelect for amdgcn.class (detail/ViewSVN)
    by arsenm
  35. [PowerPC][UpdateTestChecks] powerpc- triple support

    There are quite some old testcases with powerpc- triple,
    we should add this triple support so that we can update them with script.

    Differential Revision: (detail/ViewSVN)
    by jsji
  36. AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect

    Scalar extends to s64 can use S_BFE_{I64|U64}, but vector extends need
    to extend to the 32-bit half, and then to 64.

    I'm not sure what the line should be between what RegBankSelect
    handles, and what instruction select does, but for now I'm erring on
    the side of RegBankSelect for future post-RBS combines. (detail/ViewSVN)
    by arsenm
  37. [llvm-objdump] Match GNU objdump on symbol types shown in disassembly

    STT_OBJECT and STT_COMMON are dumped as data, not disassembled.

    Differential Revision: (detail/ViewSVN)
    by yuanfang
  38. [AMDGPU] Allow any value in unused src0 field in v_nop

    The LLVM disassembler assumes that the unused src0 operand of v_nop is
    zero. Other tools can put another value in that field, which is still
    valid. This commit fixes the LLVM disassembler to recognize such an
    encoding as v_nop, in the same way as we already do for s_getpc.

    Differential Revision:

    Change-Id: Iaf0363eae26ff92fc4ebc716216476adbff37a6f (detail/ViewSVN)
    by tpr
  39. [X86] Don't a vzext_movl in LowerBuildVectorv16i8/LowerBuildVectorv8i16 if there are no zeroes in the vector we're building.

    In LowerBuildVectorv16i8 we took care to use an any_extend if the first pair is in the lower 16-bits of the vector and no elements are 0. So bits [31:16] will be undefined. But we still emitted a vzext_movl to ensure that bits [127:32] are 0. If we don't need any zeroes we should be consistent and make all of 127:16 undefined.

    In LowerBuildVectorv8i16 we can just delete the vzext_movl code because we only use the scalar_to_vector when there are no zeroes. So the vzext_movl is always unnecessary.

    Found while investigating whether (vzext_movl (scalar_to_vector (loadi32)) patterns are necessary. At least one of the cases where they were necessary was where the loadi32 matched 32-bit aligned 16-bit extload. Seemed weird that we required vzext_movl for that case.

    Differential Revision: (detail/ViewSVN)
    by ctopper
  40. [X86] Cleanups and safety checks around the isFNEG

    This patch does a few things to start cleaning up the isFNEG function.

    -Remove the Op0/Op1 peekThroughBitcast calls that seem unnecessary. getTargetConstantBitsFromNode has its own peekThroughBitcast inside. And we have a separate peekThroughBitcast on the return value.
    -Add a check of the scalar size after the first peekThroughBitcast to ensure we haven't changed the element size and just did something like f32->i32 or f64->i64.
    -Remove an unnecessary check that Op1's type is floating point after the peekThroughBitcast. We're just going to look for a bit pattern from a constant. We don't care about its type.
    -Add VT checks on several places that consume the return value of isFNEG. Due to the peekThroughBitcasts inside, the type of the return value isn't guaranteed. So its not safe to use it to build other nodes without ensuring the type matches the type being used to build the node. We might be able to replace these checks with bitcasts instead, but I don't have a test case so a bail out check seemed better for now.

    Differential Revision: (detail/ViewSVN)
    by ctopper
  41. [AArch64] Regenerate vcvt tests. NFCI.

    Prep work for an upcoming patch (detail/ViewSVN)
    by rksimon
  42. [AArch64] Regenerate 2velem tests. NFCI.

    Prep work for an upcoming patch (detail/ViewSVN)
    by rksimon
  43. [AArch64] Regenerate merge-store tests. NFCI.

    Prep work for an upcoming patch (detail/ViewSVN)
    by rksimon
  44. [clang][NewPM] Add RUNS for tests that produce slightly different IR under new PM

    For CodeGenOpenCL/, the new PM produced a slightly different for
    loop, but this still checks for no loop unrolling as intended. This is
    committed separately from D63174. (detail/ViewSVN)
    by leonardchan
  45. [clang][NewPM] Remove exception handling before loading pgo sample profile data

    This patch ensures that SimplifyCFGPass comes before SampleProfileLoaderPass
    on PGO runs in the new PM and fixes clang/test/CodeGen/pgo-sample.c.

    Differential Revision: (detail/ViewSVN)
    by leonardchan
  46. [X86] Regenerate fast fadd reduction tests. NFCI

    Fix whitespace. (detail/ViewSVN)
    by rksimon
  47. AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1

    Try to fail for scc, since I don't think that should ever be produced. (detail/ViewSVN)
    by arsenm
  48. [bindings/go] Add debug information accessors

    Add debug information accessors, as provided in the following patches: (DILocation) metadata kind get/set debug location on a Value (DIScope)

    The API as proposed in this patch is similar to the current Value API,
    with a single root type and methods that are only valid for certain
    subclasses. I have considered just implementing generic Line() calls
    (that are valid on all DINodes that have a line) but the implementation
    of that got a bit awkward without support from the C API. I've also
    considered creating generic getters like a Metadata.DebugLoc() that
    returns a DebugLoc, but there is a mismatch between the Go DI nodes in
    the LLVM API and the actual DINode class hierarchy, so that's also hard
    to get right (without being confusing or breaking the API).

    Differential Revision: (detail/ViewSVN)
    by aykevl
  49. [analyzer] print() JSONify: ProgramPoint revision

    Summary: Now we also print out the filename with its path.

    Reviewers: NoQ

    Reviewed By: NoQ

    Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin,
                 mikhail.ramalho, Szelethus, donat.nagy, dkrupp, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by charusso
  50. Hexagon: Rename another copy of Register class

    For some reason clang is happy with the conflict, but MSVC is not. (detail/ViewSVN)
    by arsenm
  51. ARC: Fix -Wimplicit-fallthrough (detail/ViewSVN)
    by arsenm
  52. GlobalISel: Remove unsigned variant of SrcOp

    Force using Register.

    One downside is the generated register enums require explicit
    conversion. (detail/ViewSVN)
    by arsenm
  53. [analyzer] Fix JSON dumps for ExplodedNodes

    - Now we could see the `has_report` property in `trim-egraph` mode.
    - This patch also removes the trailing comma after each node.

    Reviewers: NoQ

    Reviewed By: NoQ

    Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin,
                 mikhail.ramalho, Szelethus, donat.nagy, dkrupp, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by charusso
  54. CodeGen: Introduce a class for registers

    Avoids using a plain unsigned for registers throughoug codegen.
    Doesn't attempt to change every register use, just something a little
    more than the set needed to build after changing the return type of
    MachineOperand::getReg(). (detail/ViewSVN)
    by arsenm
  55. [AMDGPU] Remove unused variable AllSGPRSpilledToVGPRs. NFC

    Removing the unused variable AllSGPRSpilledToVGPRs in
    to avoid
      error: variable 'AllSGPRSpilledToVGPRs' set but not used

    Reviewers: arsenm, nhaehnle

    Reviewed By: nhaehnle

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by bjope
  56. [OPENMP]Relax the test checks to pacify 32bit buildbots, NFC. (detail/ViewSVN)
    by abataev
  57. Hexagon: Rename Register class

    This avoids a naming conflict in a future patch. (detail/ViewSVN)
    by arsenm
  58. [InstCombine] reduce funnel-shift i16 X, X, 8 to bswap X

    Prefer the more exact intrinsic to remove a use of the input value
    and possibly make further transforms easier (we will still need
    to match patterns with funnel-shift of wider types as pieces of
    bswap, especially if we want to canonicalize to funnel-shift with
    constant shift amount). Discussed in D46760. (detail/ViewSVN)
    by spatel
  59. AMDGPU/GlobalISel: Fix RegBankSelect for s1 sext/zext/anyext

    This needs different handling if the source is known to be a valid
    condition or not. Handle turning it into shifts or a select during
    regbankselect. (detail/ViewSVN)
    by arsenm
  60. AMDGPU: Fold frame index into MUBUF

    This matters for byval uses outside of the entry block, which appear
    as copies.

    Previously, the only folding done was during selection, which could
    not see the underlying frame index. For any uses outside the entry
    block, the frame index was materialized in the entry block relative to
    the global scratch wave offset.

    This may produce worse code in cases where the offset ends up not
    fitting in the MUBUF offset field. A better heuristic would be helpfu
    for extreme frames. (detail/ViewSVN)
    by arsenm
  61. [InstCombine] add tests for funnel-shift to bswap; NFC (detail/ViewSVN)
    by spatel
  62. [CUDA][HIP] Don't set comdat attribute for CUDA device stub functions.\nDifferential Revision: (detail/ViewSVN)
    by kpyzhov
  63. AMDGPU: Cleanup checking when spills need emergency slots

    Address fixme, which should no longer be a problem since r363757. (detail/ViewSVN)
    by arsenm
  64. [InstCombine] SliceUpIllegalIntegerPHI - bail on out of range shifts

    trunc(lshr) handling - if the shift is out of range (undefined) then bail like we do for non-constant shifts.

    Fixes OSS Fuzz #15217 (detail/ViewSVN)
    by rksimon
  65. [clangd] Improve SelectionTree string representation (detail/ViewSVN)
    by sammccall
  66. [DAGCombine] visitMUL - allow shift by zero in MulByConstant.

    This can occur under certain circumstances when undefs are created later on in the constant multipliers (e.g. in this case due to SimplifyDemandedVectorElts). Its better to let the shift by zero to occur and perform any cleanup afterward.

    Fixes OSS Fuzz #15429 (detail/ViewSVN)
    by rksimon
  67. [ConstantFolding] Use hasVectorInstrinsicScalarOpd. NFC

    Use the hasVectorInstrinsicScalarOpd helper function
    in ConstantFoldVectorCall.

    Reviewers: rengolin, RKSimon, dblaikie

    Reviewed By: rengolin, RKSimon

    Subscribers: tschuett, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by bjope
  68. [Scalarizer] Add scalarizer support for smul.fix.sat

    Handle smul.fix.sat in the scalarizer. This is done by
    adding smul.fix.sat to the set of "isTriviallyVectorizable"

    The addition of smul.fix.sat in isTriviallyVectorizable and
    hasVectorInstrinsicScalarOpd can also be seen as a preparation
    to be able to use hasVectorInstrinsicScalarOpd in ConstantFolding.

    Reviewers: rengolin, RKSimon, dblaikie

    Reviewed By: rengolin

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by bjope
  69. [docs][llvm-nm] Add missing options to documentation

    There were several options missing from the documentation. This patch
    adds them as well as improving some wording and separating the Mach-O
    only options into a separate section.


    Reviewed by: MaskRay

    Differential Revision: (detail/ViewSVN)
    by jhenderson
  70. [sancov] Avoid unnecessary unique_ptr (detail/ViewSVN)
    by maskray
  71. [OpenCL] Restore ATOMIC_VAR_INIT

    We accidentally lost the ATOMIC_VAR_INIT and ATOMIC_FLAG_INIT macros
    in r363794.

    Also put the `memory_order` typedef back inside a `>= CL2.0` guard. (detail/ViewSVN)
    by svenvh
  72. [OpenCL] Remove more duplicates from opencl-c.h

    Identified the duplicate declarations using

      sort lib/Headers/opencl-c.h | uniq -c | grep '      2' (detail/ViewSVN)
    by svenvh
  73. [ARM] Add MVE interleaving load/store family.

    This adds the family of loads and stores with names like VLD20.8 and
    VST42.32, which load and store parts of multiple q-registers in such a
    way that executing both VLD20 and VLD21, or all four of VLD40..VLD43,
    will distribute 2 or 4 vectors' worth of memory data across the lanes
    of the same number of registers but in a transposed order.

    In addition to the Tablegen descriptions of the instructions
    themselves, this patch also adds encode and decode support for the
    QQPR and QQQQPR register classes (representing the range of loaded or
    stored vector registers), and tweaks to the parsing system for lists
    of vector registers to make it return the right format in this case
    (since, unlike NEON, MVE regards q-registers as primitive, and not
    just an alias for two d-registers). (detail/ViewSVN)
    by statham
  74. [docs][llvm-nm] Improve symbol code documentation

    The existing symbol code documentation was very incomplete. This patch
    adds the missing codes, and defines them based on the current code


    Reviewed by: rupprecht, mtrent, MaskRay

    Differential Revision: (detail/ViewSVN)
    by jhenderson
  75. [libcxx] [test] Read files as bytestrings to fix py3 encoding issues

    Use binary mode to read test files in libcxx LibcxxTestFormat class.
    This ensures that tests are read correctly independently of encoding,
    and therefore fixes UnicodeDecodeError when file is opened in Python 3
    that defaults to pure ASCII encoding.

    Technically this could be also fixed via conditionally appending
    encoding argument when opening the file in Python 3.  However, since
    the code in question only searches for fixed ASCII substrings reading
    it in binary mode is simpler and more universal.

    Differential Revision: (detail/ViewSVN)
    by mgorny
  76. [Support] Fix error handling in DataExtractor::get[US]LEB128

    These functions are documented as not modifying the offset argument if
    the extraction fails (just like other DataExtractor functions). However,
    while reviewing D63591 we discovered that this is not the case -- if the
    function reaches the end of the data buffer, it will just return the
    value parsed until that point and set offset to point to the end of the

    This fixes the functions to act as advertised, and adds a regression

    Reviewers: dblaikie, probinson, bkramer

    Subscribers: kristina, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by labath
  77. Follow up of rL363913. NFC.

    Minor reshuffle in AArch64 targetparser unittest, solving a potential problem
    with querying iterators too early. (detail/ViewSVN)
    by sjoerdmeijer
  78. [llvm-readobj/llvm-readelf] - Eliminate the elf-groups.x86_64 precompiled binary from the inputs.

    We do not need the elf-groups.x86_64. In one of the tests, it was
    used for no solid reason, and for the second test case we can use
    YAML input with SHT_GROUP sections.

    The patch performs a cleanup of one of the test cases, removes another
    one completely (since during the review was found out it actually
    duplicates one of the existent tests) and removes the precompiled binary.

    Differential revision: (detail/ViewSVN)
    by grimar
  79. PR42362: Fix auto deduction of template parameter packs from
    type-dependent argument packs.

    We need to strip off the PackExpansionExpr to get the real (dependent)
    type rather than an opaque DependentTy. (detail/ViewSVN)
    by rsmith
  80. [X86] Turn v16i16->v16i8 truncate+store into a any_extend+truncstore if we avx512f, but not avx512bw.

    Ideally we'd be able to represent this truncate as a any_extend to
    v16i32 and a truncate, but SelectionDAG doens't know how to not
    fold those together.

    We have isel patterns to use a vpmovzxwd+vpdmovdb for the truncate,
    but we aren't able to simultaneously fold the load and the store
    from the isel pattern. By pulling the truncate into the store we
    can successfully hide it from the DAG combiner. Then we can isel
    pattern match the truncstore and load+any_extend separately. (detail/ViewSVN)
    by ctopper
  81. [GN] Generation failure caused by trailing space in file name

    When I executed gen out/gn I got the following error:

    ERROR at //compiler-rt/lib/builtins/ Only source, header, and object files belong in the sources of a static_library. //compiler-rt/lib/builtins/emutls.c  is not one of the valid types.
          "emutls.c ",
    See //compiler-rt/lib/ which caused the file to be included.
    It turns out to be that the latest gn doesn't accept ill-format file name. And the emutls.c above has a trailing space.
    Remove the trailing space should work.

    Patch By: myhsu
    Differential Revision: (detail/ViewSVN)
    by phosek
  82. Use C++11 implementation of unique_ptr in C++03. (detail/ViewSVN)
    by ericwf
  83. Apply new meta-programming traits throughout the library.

    The new meta-programming primitives are lower cost than the old versions. This patch removes those old versions and switches libc++ to use the new ones. (detail/ViewSVN)
    by ericwf
  84. Fix typo in comment; NFC (detail/ViewSVN)
    by sanjoy
  85. [X86] Fix isel pattern that was looking for a bitcasted load. Remove what appears to be a copy/paste mistake.

    DAG combine should ensure bitcasts of loads don't exist.

    Also remove 3 patterns that are identical to the block above them. (detail/ViewSVN)
    by ctopper
  86. Fix test for 32-bit targets. (detail/ViewSVN)
    by rsmith
  87. [Tests] Autogen and improve test readability (detail/ViewSVN)
    by reames
  88. [IndVars] Remove dead instructions after folding trivial loop exit

    In rL364135, I taught IndVars to fold exiting branches in loops with a zero backedge taken count (i.e. loops that only run one iteration).  This extends that to eliminate the dead comparison left around. (detail/ViewSVN)
    by reames
  89. SlotIndexes: delete unused functions (detail/ViewSVN)
    by maskray
  90. [InstCombine] squash is-power-of-2 that uses ctpop

    This is another intermediate IR step towards solving PR42314:

    We can test if a value is power-of-2-or-0 using ctpop(X) < 2,
    so combining that with a non-zero check of the input is the
    same as testing if exactly 1 bit is set:

    (X != 0) && (ctpop(X) u< 2) --> ctpop(X) == 1

    Differential Revision: (detail/ViewSVN)
    by spatel
  91. SlotIndexes: simplify IdxMBBPair operators (detail/ViewSVN)
    by maskray
  92. [SelectionDAG] Remove the code that attempts to calculate the alignment for the second half of a split masked load/store.

    The code divides the alignment by 2 if the original alignment is
    equal to the original VT size. But this wouldn't be correct
    if the alignment was larger than the VT size.

    The memory operand object already takes care of calling MinAlign
    on the base alignment and the memory pointer offset. So we don't
    need any special code at all. (detail/ViewSVN)
    by ctopper
  93. [X86][SelectionDAG] Cleanup and simplify masked_load/masked_store in tablegen. Use more precise PatFrags for scalar masked load/store.

    Rename masked_load/masked_store to masked_ld/masked_st to discourage
    their direct use. We need to check truncating/extending and
    compressing/expanding before using them. This revealed that
    our scalar masked load/store patterns were misusing these.

    With those out of the way, renamed masked_load_unaligned and
    masked_store_unaligned to remove the "_unaligned". We didn't
    check the alignment anyway so the name was somewhat misleading.

    Make the aligned versions inherit from masked_load/store instead
    from a separate identical version. Merge the 3 different alignments
    PatFrags into a single version that uses the VT from the SDNode to
    determine the size that the alignment needs to match. (detail/ViewSVN)
    by ctopper
  94. Disable test by default (detail/ViewSVN)
    by ericwf
  95. Add super fast _IsSame trait for internal use.

    Clang provides __is_same that doesn't produce any instantiations
    and just returns a bool. It's a lot faster than using std::is_same

    I'll follow up with a patch to actually start using it. (detail/ViewSVN)
    by ericwf
  96. Revert "builtins: relax __iso_volatile_{load,store}32"

    This reverts commit SVN r364137.  This seems to be cause problems with
    casting in C. (detail/ViewSVN)
    by Saleem Abdulrasool
  97. Add noexcept throughout <atomic>

    The CMake CheckLibcxxAtomic module was always failing to compile
    the example, even when libatomic wasn't needed. This was caused
    because the check doesn't link a C++ runtime library to provide
    std::terminate, which is required for exception support.

    The check is still really broken, but <atomic> is better! (detail/ViewSVN)
    by ericwf
  98. MSVC visualizers for type aliases

    For example, the following TypeAliasTemplateDecl now displays in the autos window as
    template<class T> using type_identity_t = type_identity<T>::type; (detail/ViewSVN)
    by mps
  99. Fix placement of -Wno-ignored-attributes (detail/ViewSVN)
    by ericwf
  100. [Support] Fix build under Emscripten

    Emscripten's libc doesn't define MNT_LOCAL, thus causing a build
    failure in the fallback path. However, to the best of my knowledge,
    it also doesn't support remote file system mounts, so we may simply
    return `true` here (as we do for e.g. Fuchsia). With this fix, the
    core LLVM libraries build correctly under emscripten (though some
    of the tools and utils do not).

    Reviewers: kripken
    Differential Revision: (detail/ViewSVN)
    by kfischer
  101. Disable -Wignored-attributes for now (detail/ViewSVN)
    by ericwf
  102. Revert [CommandLine] Remove OptionCategory and SubCommand caches from the Option class.

    This reverts r364134 (git commit a5b83bc9e3b8e8945b55068c762bd6c73621a4b0)

    Caused errors in the asan bot, so the GeneralCategory global needs to
    be changed to ManagedStatic.

    Differential Revision: (detail/ViewSVN)
    by dhinton
  103. Fix TBAA representation for zero-sized fields and unnamed bit-fields.

    Unnamed bit-fields should not be represented in the TBAA metadata
    because they do not represent storage fields (they only affect layout).

    Zero-sized fields should not be represented in the TBAA metadata
    because by definition they have no associated storage (so we will never
    emit a load or store through them), and they might not appear in
    declaration order within the struct layout.

    Fixes a verifier failure when emitting a TBAA-enabled load through a
    class type containing a zero-sized field. (detail/ViewSVN)
    by rsmith
  104. Remove reliance on toCharUnitsFromBits rounding down. (detail/ViewSVN)
    by rsmith
  105. Natural MSVC visualization of constructors

    E.g., Allow MSVC to visualize a CXXConstructorDecl like
    Constructor { Y(type_identity_t<T>)} (detail/ViewSVN)
    by mps
  106. builtins: relax __iso_volatile_{load,store}32

    This is reduced from MSVC's MSVCPRT 14.21.27702 atomic header.  Because
    Windows is a LLP64 environment, `long`, `long int`, and `int` are all
    synonymous.  Change the signature for `__iso_volatile_load32` and
    `__iso_volatile_store32` to accept a `long int` instead.  This allows
    an implicit cast of `int` to `long int` while also permitting `long`
    to be accepted. (detail/ViewSVN)
    by Saleem Abdulrasool
  107. [X86][SSE] Fold extract_subvector(vselect(x,y,z),0) -> vselect(extract_subvector(x,0),extract_subvector(y,0),extract_subvector(z,0)) (detail/ViewSVN)
    by rksimon
  108. Exploit a zero LoopExit count to eliminate loop exits

    This turned out to be surprisingly effective. I was originally doing this just for completeness sake, but it seems like there are a lot of cases where SCEV's exit count reasoning is stronger than it's isKnownPredicate reasoning.

    Once this is in, I'm thinking about trying to build on the same infrastructure to eliminate provably untaken checks. There may be something generally interesting here.

    Differential Revision: (detail/ViewSVN)
    by reames
  109. [CommandLine] Remove OptionCategory and SubCommand caches from the Option class.

    This change processes `OptionCategory`s and `SubCommand`s as they
    are seen instead of caching them in the Option class and processing
    them later.  Doing so simplifies the work needed to be done by the Global
    parser and significantly reduces the size of the Option class to a mere 64

    Removing  the `OptionCategory` cache saved 24 bytes, and removing
    the `SubCommand` cache saved an additional 48 bytes, for a total of a
    72 byte reduction.

    Reviewers: beanz, zturner, MaskRay, serge-sans-paille

    Reviewed By: serge-sans-paille

    Subscribers: serge-sans-paille, tstellar, zturner, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by dhinton
  110. [NFC] Fix indentation in PPCAsmPrinter.cpp

    After r248261, the indentation switches, inside a namespace definition,
    between indenting and not indenting one level in for that namespace; the
    abomination occurs in the middle of a class definition. Fix that. (detail/ViewSVN)
    by hubert.reinterpretcast
  111. [PowerPC][NFC] Move comment to the relevant function

    A comment that applies to a virtual destructor was placed on a class
    constructor. Move the comment to where it belongs. (detail/ViewSVN)
    by hubert.reinterpretcast
  112. PDB docs: Delete trailing whitespace, wrap to 80 cols (detail/ViewSVN)
    by nico
  113. [NewGVN] Fix copy/paste mistake in cast (detail/ViewSVN)
    by nikic
  114. [NewGVN] Remove dead SwitchEdges variable; NFC (detail/ViewSVN)
    by nikic
  115. [LFTR] Add tests for PR41998; NFC

    The limit for the pointer case is incorrect. (detail/ViewSVN)
    by nikic
  116. [X86] Don't use _MM_FROUND_CUR_DIRECTION in the intrinsics tests.

    _MM_FROUND_CUR_DIRECTION is the behavior of the intrinsics that
    don't take a rounding mode argument. So a better test
    is using _MM_FROUND_NO_EXC with the SAE only intrinsics and
    an explicit rounding mode with the intrinsics that support
    embedded rounding mode. (detail/ViewSVN)
    by ctopper
  117. AArch64: Add support for reading pc using llvm.read_register.

    This is useful for allowing code to efficiently take an address
    that can be later mapped onto debug info. Currently the hwasan
    pass achieves this by taking the address of the current function:

    but this costs two instructions (plus a GOT entry in PIC code) per function
    with stack variables. This will allow the cost to be reduced to a single

    Differential Revision: (detail/ViewSVN)
    by pcc
  118. [CMake] Delete redundant DEPENDS/LINK_LIBS from LineEditor/XRay

    The link dependencies are already specified in LLVMBuild.txt (detail/ViewSVN)
    by maskray
  119. Make GlobalISel depend on SelectionDAG after D63169

    GlobalISel/IRTranslator.cpp now references SelectionDAG/FunctionLoweringInfo.cpp.
    This fixes a link error in -DBUILD_SHARED_LIBS=on builds:

        ld.lld: error: undefined symbol: llvm::FunctionLoweringInfo::clear()
        >>> referenced by IRTranslator.cpp:2198 (../lib/CodeGen/GlobalISel/IRTranslator.cpp:2198)
        >>>               lib/CodeGen/GlobalISel/CMakeFiles/LLVMGlobalISel.dir/IRTranslator.cpp.o:(llvm::IRTranslator::finalizeFunction()) (detail/ViewSVN)
    by maskray
  120. AMDGPU: Fix target builtins for gfx10

    This wasn't setting some of the features from older generations. (detail/ViewSVN)
    by arsenm
  121. Fix UNSUPPORTED attribute from windows to system-windows. (detail/ViewSVN)
    by dyung
  122. [llvm-objdump] Allow --disassemble-functions to take demangled names

    The --disassemble-functions switch takes demangled names when
    --demangle is specified, otherwise the switch takes mangled names.

    Reviewers: jhenderson, grimar, MaskRay, rupprecht

    Differential Revision: (detail/ViewSVN)
    by yuanfang
  123. [NFC] Marking test added in r363975 as unsupported on Windows.

    This test references a path that does not exist on Windows causing
    it to emit different output from what was expected leading to a
    failure when run on Windows. (detail/ViewSVN)
    by dyung

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 17806
originally caused by:

This run spent:

  • 21 min waiting;
  • 17 hr build duration;
  • 18 hr total from scheduled to completion.

Identified problems

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 1

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Indication 2

Ninja target failed

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Indication 3

Compile Error

This build failed because of a compile error. Below is a list of all errors in the build log:
Indication 4