FailedChanges

Summary

  1. [X86] Add broadcast load unfold support for smin/umin/smax/umax.
  2. [X86] Add broadcast load unfolding tests for smin/umin/smax/smin.
  3. AMDGPU: Remove pointless wrapper nodes for init.exec intrinsics
  4. [X86] Add broadcast load unfolding support for VMAXPS/PD and VMINPS/PD.
  5. [X86] Add broadcast load unfolding tests for vmaxps/pd and vminps/pd
  6. [X86] Add fp128 test cases for ceil/floor/trunc/nearbyint/rint/round libcalls.
  7. [MachineCopyPropagation] Remove redundant copies after TailDup via machine-cp Summary: After tailduplication, we have redundant copies. We can remove these copies in machine-cp if it's safe to, i.e. ``` $reg0 = OP ... ... <<< No read or clobber of $reg0 and $reg1 $reg1 = COPY $reg0 <<< $reg0 is killed ... <RET> ``` will be transformed to ``` $reg1 = OP ... ... <RET> ``` Differential Revision: https://reviews.llvm.org/D65267
  8. [X86] Add test cases for fptoui/fptosi/sitofp/uitofp between fp128 and i128.
  9. [X86] Use xorps to create fp128 +0.0 constants. This matches what we do for f32/f64. gcc also does this for fp128.
  10. [X86] Add avx and avx512f RUN lines to fp128-cast.ll
  11. Relax opcode checks in test to check for only a number instead of a specific number.
  12. Enable LSan for NetBSD/i386 in test/asan/lit.cfg.py
  13. [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add faux shuffle support. This patch decodes target and faux shuffles with getTargetShuffleInputs - a reduced version of resolveTargetShuffleInputs that doesn't resolve SM_SentinelZero cases, so we can correctly remove zero vectors if they aren't demanded.
  14. [InstCombine][NFC] Some tests for usub overflow+nonzero check improvement (PR43251) https://rise4fun.com/Alive/kHq https://bugs.llvm.org/show_bug.cgi?id=43251
  15. [X86] Add a hack to combineVSelectWithAllOnesOrZeros to turn selects with two zero/undef vector inputs into an all zeroes vector. If the two zero vectors have undefs in different places they won't get combined by simplifySelect. This fixes a regression from an earlier commit.
  16. [X86] Remove call to getZeroVector from materializeVectorConstant. Add isel patterns for zero vectors with all types. The change to avx512-vec-cmp.ll is a regression, but should be easy to fix. It occurs because the getZeroVector call was canonicalizing both sides to the same node, then SimplifySelect was able to simplify it. But since only called getZeroVector on some VTs this isn't a robust way to combine this. The change to vector-shuffle-combining-ssse3.ll is more instructions, but removes a constant pool load so its unclear if its a regression or not.
  17. [InstSimplify] simplifyUnsignedRangeCheck(): if we know that X != 0, handle more cases (PR43246) Summary: This is motivated by D67122 sanitizer check enhancement. That patch seemingly worsens `-fsanitize=pointer-overflow` overhead from 25% to 50%, which strongly implies missing folds. In this particular case, given ``` char* test(char& base, unsigned long offset) { return &base + offset; } ``` it will end up producing something like https://godbolt.org/z/LK5-iH which after optimizations reduces down to roughly ``` define i1 @t0(i8* nonnull %base, i64 %offset) { %base_int = ptrtoint i8* %base to i64 %adjusted = add i64 %base_int, %offset %non_null_after_adjustment = icmp ne i64 %adjusted, 0 %no_overflow_during_adjustment = icmp uge i64 %adjusted, %base_int %res = and i1 %non_null_after_adjustment, %no_overflow_during_adjustment ret i1 %res } ``` Without D67122 there was no `%non_null_after_adjustment`, and in this particular case we can get rid of the overhead: Here we add some offset to a non-null pointer, and check that the result does not overflow and is not a null pointer. But since the base pointer is already non-null, and we check for overflow, that overflow check will already catch the null pointer, so the separate null check is redundant and can be dropped. Alive proofs: https://rise4fun.com/Alive/WRzq There are more patterns of "unsigned-add-with-overflow", they are not handled here, but this is the main pattern, that we currently consider canonical, so it makes sense to handle it. https://bugs.llvm.org/show_bug.cgi?id=43246 Reviewers: spatel, nikic, vsk Reviewed By: spatel Subscribers: hiraditya, llvm-commits, reames Tags: #llvm Differential Revision: https://reviews.llvm.org/D67332
  18. [InstCombine] add tests for icmp with srem operand; NFC
  19. [X86] X86DAGToDAGISel::combineIncDecVector(): call getSplatBuildVector() manually As reported in post-commit review of r370327, there is some case where the code crashes. As discussed with Craig Topper, the problem is that getConstant() internally calls getSplatBuildVector(), so we don't insert the constant itself. If we do that manually we're good.
  20. [X86] Use DAG.getConstant instead of getZeroVector in combinePMULDQ. getZeroVector canonicalizes the type to vXi32, but that's a legalization action. We should use the most correct type if possible.
  21. [DAGCombiner][X86][ARM] Teach visitMULO to fold multiplies with 0 to 0 and no carry. I modified the ARM test to use two inputs instead of 0 so the test hopefully still tests what was intended.
  22. [X86] Teach materializeVectorConstant to not call getZeroVector/getOnesVector on the types we already have isel patterns for.
  23. Move prop-sink branch to monorepo.
  24. [InstCombine] fold extract+insert into identity shuffle This is similar to the existing fold for splats added with: rL365379 If we can adjust the shuffle mask to include another element in an identity mask (if it changes vector length, that's an extract/insert subvector operation in the backend), then that can eliminate extractelement/insertelement pairs in IR. All targets are expected to lower shuffles with identity masks efficiently.
  25. [NFC][InstSimplify] Some tests for dropping null check after uadd.with.overflow of non-null (PR43246) https://rise4fun.com/Alive/WRzq Name: C <= Y && Y != 0 --> C <= Y iff C != 0 Pre: C != 0 %y_is_nonnull = icmp ne i64 %y, 0 %no_overflow = icmp ule i64 C, %y %r = and i1 %y_is_nonnull, %no_overflow => %r = %no_overflow Name: C <= Y || Y != 0 --> Y != 0 iff C != 0 Pre: C != 0 %y_is_nonnull = icmp ne i64 %y, 0 %no_overflow = icmp ule i64 C, %y %r = or i1 %y_is_nonnull, %no_overflow => %r = %y_is_nonnull Name: C > Y || Y == 0 --> C > Y iff C != 0 Pre: C != 0 %y_is_null = icmp eq i64 %y, 0 %overflow = icmp ugt i64 C, %y %r = or i1 %y_is_null, %overflow => %r = %overflow Name: C > Y && Y == 0 --> Y == 0 iff C != 0 Pre: C != 0 %y_is_null = icmp eq i64 %y, 0 %overflow = icmp ugt i64 C, %y %r = and i1 %y_is_null, %overflow => %r = %y_is_null https://bugs.llvm.org/show_bug.cgi?id=43246
  26. Enable LSan tests for NetBSD/i386
  27. Stop marking 5 ASan tests as failing on NetBSD/i386 Unexpected Passing Tests (4): AddressSanitizer-i386-netbsd :: TestCases/Posix/coverage-reset.cpp AddressSanitizer-i386-netbsd :: TestCases/Posix/coverage.cpp AddressSanitizer-i386-netbsd :: TestCases/Posix/interception-in-shared-lib-test.cpp AddressSanitizer-i386-netbsd :: TestCases/suppressions-library.cpp
  28. [ASan] Only run dlopen-mixed-c-cxx.c with static runtime This is what the original bug (http://llvm.org/PR39641) and the fix in https://reviews.llvm.org/D63877 have been about. With the dynamic runtime the test only passes when the asan library is linked against libstdc++: In contrast to libc++abi, it does not implement __cxa_rethrow_primary_exception so the regex matches the line saying that asan cannot intercept this function. Indeed, there is no message that the runtime failed to intercept __cxa_throw. Differential Revision: https://reviews.llvm.org/D67298
  29. Enable leak-detection for NetBSD/amd64 in test/asan
  30. Do not intercept malloc_usable_size on NetBSD
  31. [DebugInfo][X86] Describe call site values for zero-valued imms Summary: Add zero-materializing XORs to X86's describeLoadedValue() hook in order to produce call site values. I have had to change the defs logic in collectCallSiteParameters() a bit to be able to describe the XORs. The XORs implicitly define $eflags, which would cause them to never be considered, due to a guard condition that I->getNumDefs() is one. I have changed that condition so that we now only consider instructions where a forwarded register overlaps with the instruction's single explicit define. We still need to collect the implicit defines of other forwarded registers to remove them from the work list. I'm not sure how to move towards supporting instructions with multiple explicit defines, cases where forwarded register are implicitly defined, and/or cases where an instruction produces values for multiple forwarded registers. Perhaps the describeLoadedValue() hook should take a register argument, and we then leave it up to the hook to describe the loaded value in that register? I have not yet encountered a situation where that would be necessary though. Reviewers: aprantl, vsk, djtodoro, NikolaPrica Reviewed By: vsk Subscribers: ychen, hiraditya, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D67225
  32. [NFC] Make the describeLoadedValue() hook return machine operand objects Summary: This changes the ParamLoadedValue pair which the describeLoadedValue() hook returns so that MachineOperand objects are returned instead of pointers. When describing call site values we may need to describe operands which are not part of the instruction. One such example is zero-materializing XORs on x86, which I have implemented support for in a child revision. Instead of having to return a pointer to an operand stored somewhere outside the instruction, start returning objects directly instead, as that simplifies the code. The MachineOperand class only holds POD members, and on x86-64 it is 32 bytes large. That combined with copy elision means that the overhead of returning a machine operand object from the hook does not become very large. I benchmarked this on a 8-thread i7-8650U machine with 32 GB RAM. The benchmark consisted of building a clang 8.0 binary configured with: -DCMAKE_BUILD_TYPE=RelWithDebInfo \ -DLLVM_TARGETS_TO_BUILD=X86 \ -DLLVM_USE_SANITIZER=Address \ -DCMAKE_CXX_FLAGS="-Xclang -femit-debug-entry-values -stdlib=libc++" The average wall clock time increased by 4 seconds, from 62:05 to 62:09, which is an 0.1% increase. Reviewers: aprantl, vsk, djtodoro, NikolaPrica Reviewed By: vsk Subscribers: hiraditya, ychen, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D67261
Revision 371366 by ctopper:
[X86] Add broadcast load unfold support for smin/umin/smax/umax.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFoldTables.cpp (diff)llvm.src/lib/Target/X86/X86InstrFoldTables.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-broadcast-unfold.ll (diff)llvm.src/test/CodeGen/X86/avx512-broadcast-unfold.ll
Revision 371365 by ctopper:
[X86] Add broadcast load unfolding tests for smin/umin/smax/smin.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-broadcast-unfold.ll (diff)llvm.src/test/CodeGen/X86/avx512-broadcast-unfold.ll
Revision 371364 by arsenm:
AMDGPU: Remove pointless wrapper nodes for init.exec intrinsics
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.td (diff)llvm.src/include/llvm/IR/IntrinsicsAMDGPU.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h (diff)llvm.src/lib/Target/AMDGPU/AMDGPUISelLowering.h
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.td (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (diff)llvm.src/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SIInstructions.td
Revision 371363 by ctopper:
[X86] Add broadcast load unfolding support for VMAXPS/PD and VMINPS/PD.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFoldTables.cpp (diff)llvm.src/lib/Target/X86/X86InstrFoldTables.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-broadcast-unfold.ll (diff)llvm.src/test/CodeGen/X86/avx512-broadcast-unfold.ll
Revision 371362 by ctopper:
[X86] Add broadcast load unfolding tests for vmaxps/pd and vminps/pd
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-broadcast-unfold.ll (diff)llvm.src/test/CodeGen/X86/avx512-broadcast-unfold.ll
Revision 371360 by ctopper:
[X86] Add fp128 test cases for ceil/floor/trunc/nearbyint/rint/round libcalls.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/fp128-libcalls.ll (diff)llvm.src/test/CodeGen/X86/fp128-libcalls.ll
Revision 371359 by lkail:
[MachineCopyPropagation] Remove redundant copies after TailDup via machine-cp

Summary:
After tailduplication, we have redundant copies. We can remove these
copies in machine-cp if it's safe to, i.e.
```
$reg0 = OP ...
... <<< No read or clobber of $reg0 and $reg1
$reg1 = COPY $reg0 <<< $reg0 is killed
...
<RET>
```
will be transformed to
```
$reg1 = OP ...
...
<RET>
```

Differential Revision: https://reviews.llvm.org/D65267
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp (diff)llvm.src/lib/CodeGen/MachineCopyPropagation.cpp
The file was modified/llvm/trunk/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll (diff)llvm.src/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
The file was modified/llvm/trunk/test/CodeGen/X86/mul-i512.ll (diff)llvm.src/test/CodeGen/X86/mul-i512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/umulo-128-legalisation-lowering.ll (diff)llvm.src/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
Revision 371358 by ctopper:
[X86] Add test cases for fptoui/fptosi/sitofp/uitofp between fp128 and i128.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/fp128-cast.ll (diff)llvm.src/test/CodeGen/X86/fp128-cast.ll
Revision 371357 by ctopper:
[X86] Use xorps to create fp128 +0.0 constants.

This matches what we do for f32/f64. gcc also does this for fp128.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.td (diff)llvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (diff)llvm.src/lib/Target/X86/X86InstrFragmentsSIMD.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (diff)llvm.src/lib/Target/X86/X86InstrInfo.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.td (diff)llvm.src/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/test/CodeGen/X86/fp128-cast.ll (diff)llvm.src/test/CodeGen/X86/fp128-cast.ll
Revision 371356 by ctopper:
[X86] Add avx and avx512f RUN lines to fp128-cast.ll
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/fp128-cast.ll (diff)llvm.src/test/CodeGen/X86/fp128-cast.ll
Revision 371355 by dyung:
Relax opcode checks in test to check for only a number instead of a specific number.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (diff)llvm.src/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Revision 371354 by kamil:
Enable LSan for NetBSD/i386 in test/asan/lit.cfg.py
Change TypePath in RepositoryPath in Workspace
The file was modified/compiler-rt/trunk/test/asan/lit.cfg.py (diff)compiler-rt.src/test/asan/lit.cfg.py
Revision 371353 by rksimon:
[X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add faux shuffle support.

This patch decodes target and faux shuffles with getTargetShuffleInputs - a reduced version of resolveTargetShuffleInputs that doesn't resolve SM_SentinelZero cases, so we can correctly remove zero vectors if they aren't demanded.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-mul.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-mul.ll
Revision 371352 by lebedevri:
[InstCombine][NFC] Some tests for usub overflow+nonzero check improvement (PR43251)

https://rise4fun.com/Alive/kHq

https://bugs.llvm.org/show_bug.cgi?id=43251
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The file was added/llvm/trunk/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.llllvm.src/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
Revision 371351 by ctopper:
[X86] Add a hack to combineVSelectWithAllOnesOrZeros to turn selects with two zero/undef vector inputs into an all zeroes vector.

If the two zero vectors have undefs in different places they
won't get combined by simplifySelect.

This fixes a regression from an earlier commit.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll (diff)llvm.src/test/CodeGen/X86/avx512-vec-cmp.ll
Revision 371350 by ctopper:
[X86] Remove call to getZeroVector from materializeVectorConstant. Add isel patterns for zero vectors with all types.

The change to avx512-vec-cmp.ll is a regression, but should be
easy to fix. It occurs because the getZeroVector call was
canonicalizing both sides to the same node, then SimplifySelect
was able to simplify it. But since only called getZeroVector
on some VTs this isn't a robust way to combine this.

The change to vector-shuffle-combining-ssse3.ll is more
instructions, but removes a constant pool load so its unclear
if its a regression or not.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.td (diff)llvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.td (diff)llvm.src/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll (diff)llvm.src/test/CodeGen/X86/avx512-vec-cmp.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll (diff)llvm.src/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
Revision 371349 by lebedevri:
[InstSimplify] simplifyUnsignedRangeCheck(): if we know that X != 0, handle more cases (PR43246)

Summary:
This is motivated by D67122 sanitizer check enhancement.
That patch seemingly worsens `-fsanitize=pointer-overflow`
overhead from 25% to 50%, which strongly implies missing folds.

In this particular case, given
```
char* test(char& base, unsigned long offset) {
  return &base + offset;
}
```
it will end up producing something like
https://godbolt.org/z/LK5-iH
which after optimizations reduces down to roughly
```
define i1 @t0(i8* nonnull %base, i64 %offset) {
  %base_int = ptrtoint i8* %base to i64
  %adjusted = add i64 %base_int, %offset
  %non_null_after_adjustment = icmp ne i64 %adjusted, 0
  %no_overflow_during_adjustment = icmp uge i64 %adjusted, %base_int
  %res = and i1 %non_null_after_adjustment, %no_overflow_during_adjustment
  ret i1 %res
}
```
Without D67122 there was no `%non_null_after_adjustment`,
and in this particular case we can get rid of the overhead:

Here we add some offset to a non-null pointer,
and check that the result does not overflow and is not a null pointer.
But since the base pointer is already non-null, and we check for overflow,
that overflow check will already catch the null pointer,
so the separate null check is redundant and can be dropped.

Alive proofs:
https://rise4fun.com/Alive/WRzq

There are more patterns of "unsigned-add-with-overflow", they are not handled here,
but this is the main pattern, that we currently consider canonical,
so it makes sense to handle it.

https://bugs.llvm.org/show_bug.cgi?id=43246

Reviewers: spatel, nikic, vsk

Reviewed By: spatel

Subscribers: hiraditya, llvm-commits, reames

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67332
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The file was modified/llvm/trunk/lib/Analysis/InstructionSimplify.cpp (diff)llvm.src/lib/Analysis/InstructionSimplify.cpp
The file was modified/llvm/trunk/test/Transforms/InstSimplify/redundant-null-check-in-uadd_with_overflow-of-nonnull-ptr.ll (diff)llvm.src/test/Transforms/InstSimplify/redundant-null-check-in-uadd_with_overflow-of-nonnull-ptr.ll
Revision 371348 by spatel:
[InstCombine] add tests for icmp with srem operand; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/icmp-div-constant.ll (diff)llvm.src/test/Transforms/InstCombine/icmp-div-constant.ll
Revision 371346 by lebedevri:
[X86] X86DAGToDAGISel::combineIncDecVector(): call getSplatBuildVector() manually

As reported in post-commit review of r370327,
there is some case where the code crashes.

As discussed with Craig Topper, the problem is that getConstant()
internally calls getSplatBuildVector(), so we don't insert
the constant itself.

If we do that manually we're good.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (diff)llvm.src/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was added/llvm/trunk/test/CodeGen/X86/combineIncDecVector-crash.llllvm.src/test/CodeGen/X86/combineIncDecVector-crash.ll
Revision 371345 by ctopper:
[X86] Use DAG.getConstant instead of getZeroVector in combinePMULDQ.

getZeroVector canonicalizes the type to vXi32, but that's a
legalization action. We should use the most correct type if
possible.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
Revision 371344 by ctopper:
[DAGCombiner][X86][ARM] Teach visitMULO to fold multiplies with 0 to 0 and no carry.

I modified the ARM test to use two inputs instead of 0 so the
test hopefully still tests what was intended.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff)llvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/test/CodeGen/ARM/select.ll (diff)llvm.src/test/CodeGen/ARM/select.ll
The file was modified/llvm/trunk/test/CodeGen/X86/xmulo.ll (diff)llvm.src/test/CodeGen/X86/xmulo.ll
Revision 371343 by ctopper:
[X86] Teach materializeVectorConstant to not call getZeroVector/getOnesVector on the types we already have isel patterns for.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/fold-load-vec.ll (diff)llvm.src/test/CodeGen/X86/fold-load-vec.ll
Revision 371342 by boga95:
Move prop-sink branch to monorepo.
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The file was modified/cfe/trunk/lib/StaticAnalyzer/Checkers/GenericTaintChecker.cpp (diff)clang.src/lib/StaticAnalyzer/Checkers/GenericTaintChecker.cpp
The file was modified/cfe/trunk/test/Analysis/taint-generic.c (diff)clang.src/test/Analysis/taint-generic.c
Revision 371340 by spatel:
[InstCombine] fold extract+insert into identity shuffle

This is similar to the existing fold for splats added with:
rL365379

If we can adjust the shuffle mask to include another element
in an identity mask (if it changes vector length, that's an
extract/insert subvector operation in the backend), then that
can eliminate extractelement/insertelement pairs in IR.

All targets are expected to lower shuffles with identity masks
efficiently.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineVectorOps.cpp (diff)llvm.src/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/insert-extract-shuffle.ll (diff)llvm.src/test/Transforms/InstCombine/insert-extract-shuffle.ll
Revision 371339 by lebedevri:
[NFC][InstSimplify] Some tests for dropping null check after uadd.with.overflow of non-null (PR43246)

https://rise4fun.com/Alive/WRzq

Name: C <= Y && Y != 0  -->  C <= Y  iff C != 0
Pre: C != 0
  %y_is_nonnull = icmp ne i64 %y, 0
  %no_overflow = icmp ule i64 C, %y
  %r = and i1 %y_is_nonnull, %no_overflow
=>
  %r = %no_overflow

Name: C <= Y || Y != 0  -->  Y != 0  iff C != 0
Pre: C != 0
  %y_is_nonnull = icmp ne i64 %y, 0
  %no_overflow = icmp ule i64 C, %y
  %r = or i1 %y_is_nonnull, %no_overflow
=>
  %r = %y_is_nonnull

Name: C > Y || Y == 0  -->  C > Y  iff C != 0
Pre: C != 0
  %y_is_null = icmp eq i64 %y, 0
  %overflow = icmp ugt i64 C, %y
  %r = or i1 %y_is_null, %overflow
=>
  %r = %overflow

Name: C > Y && Y == 0  -->  Y == 0  iff C != 0
Pre: C != 0
  %y_is_null = icmp eq i64 %y, 0
  %overflow = icmp ugt i64 C, %y
  %r = and i1 %y_is_null, %overflow
=>
  %r = %y_is_null

https://bugs.llvm.org/show_bug.cgi?id=43246
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The file was added/llvm/trunk/test/Transforms/InstSimplify/redundant-null-check-in-uadd_with_overflow-of-nonnull-ptr.llllvm.src/test/Transforms/InstSimplify/redundant-null-check-in-uadd_with_overflow-of-nonnull-ptr.ll
Revision 371338 by kamil:
Enable LSan tests for NetBSD/i386
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The file was modified/compiler-rt/trunk/test/lsan/lit.common.cfg.py (diff)compiler-rt.src/test/lsan/lit.common.cfg.py
Revision 371337 by kamil:
Stop marking 5 ASan tests as failing on NetBSD/i386

Unexpected Passing Tests (4):
    AddressSanitizer-i386-netbsd :: TestCases/Posix/coverage-reset.cpp
    AddressSanitizer-i386-netbsd :: TestCases/Posix/coverage.cpp
    AddressSanitizer-i386-netbsd :: TestCases/Posix/interception-in-shared-lib-test.cpp
    AddressSanitizer-i386-netbsd :: TestCases/suppressions-library.cpp
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The file was modified/compiler-rt/trunk/test/asan/TestCases/Posix/coverage-reset.cpp (diff)compiler-rt.src/test/asan/TestCases/Posix/coverage-reset.cpp
The file was modified/compiler-rt/trunk/test/asan/TestCases/Posix/coverage.cpp (diff)compiler-rt.src/test/asan/TestCases/Posix/coverage.cpp
The file was modified/compiler-rt/trunk/test/asan/TestCases/Posix/interception-in-shared-lib-test.cpp (diff)compiler-rt.src/test/asan/TestCases/Posix/interception-in-shared-lib-test.cpp
The file was modified/compiler-rt/trunk/test/asan/TestCases/suppressions-library.cpp (diff)compiler-rt.src/test/asan/TestCases/suppressions-library.cpp
Revision 371336 by hahnfeld:
[ASan] Only run dlopen-mixed-c-cxx.c with static runtime

This is what the original bug (http://llvm.org/PR39641) and the fix
in https://reviews.llvm.org/D63877 have been about.
With the dynamic runtime the test only passes when the asan library
is linked against libstdc++: In contrast to libc++abi, it does not
implement __cxa_rethrow_primary_exception so the regex matches the
line saying that asan cannot intercept this function. Indeed, there
is no message that the runtime failed to intercept  __cxa_throw.

Differential Revision: https://reviews.llvm.org/D67298
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The file was modified/compiler-rt/trunk/test/asan/TestCases/Linux/dlopen-mixed-c-cxx.c (diff)compiler-rt.src/test/asan/TestCases/Linux/dlopen-mixed-c-cxx.c
Revision 371335 by kamil:
Enable leak-detection for NetBSD/amd64 in test/asan
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The file was modified/compiler-rt/trunk/test/asan/lit.cfg.py (diff)compiler-rt.src/test/asan/lit.cfg.py
Revision 371334 by kamil:
Do not intercept malloc_usable_size on NetBSD
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The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_platform_interceptors.h (diff)compiler-rt.src/lib/sanitizer_common/sanitizer_platform_interceptors.h
Revision 371333 by dstenb:
[DebugInfo][X86] Describe call site values for zero-valued imms

Summary:
Add zero-materializing XORs to X86's describeLoadedValue() hook in order
to produce call site values.

I have had to change the defs logic in collectCallSiteParameters() a bit
to be able to describe the XORs. The XORs implicitly define $eflags,
which would cause them to never be considered, due to a guard condition
that I->getNumDefs() is one. I have changed that condition so that we
now only consider instructions where a forwarded register overlaps with
the instruction's single explicit define. We still need to collect the implicit
defines of other forwarded registers to remove them from the work list.
I'm not sure how to move towards supporting instructions with multiple
explicit defines, cases where forwarded register are implicitly defined,
and/or cases where an instruction produces values for multiple forwarded
registers. Perhaps the describeLoadedValue() hook should take a register
argument, and we then leave it up to the hook to describe the loaded
value in that register? I have not yet encountered a situation where
that would be necessary though.

Reviewers: aprantl, vsk, djtodoro, NikolaPrica

Reviewed By: vsk

Subscribers: ychen, hiraditya, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D67225
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The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (diff)llvm.src/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (diff)llvm.src/lib/Target/X86/X86InstrInfo.cpp
The file was added/llvm/trunk/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.llllvm.src/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
Revision 371332 by dstenb:
[NFC] Make the describeLoadedValue() hook return machine operand objects

Summary:
This changes the ParamLoadedValue pair which the describeLoadedValue()
hook returns so that MachineOperand objects are returned instead of
pointers.

When describing call site values we may need to describe operands which
are not part of the instruction. One such example is zero-materializing
XORs on x86, which I have implemented support for in a child revision.
Instead of having to return a pointer to an operand stored somewhere
outside the instruction, start returning objects directly instead, as
that simplifies the code.

The MachineOperand class only holds POD members, and on x86-64 it is 32
bytes large. That combined with copy elision means that the overhead of
returning a machine operand object from the hook does not become very
large.

I benchmarked this on a 8-thread i7-8650U machine with 32 GB RAM. The
benchmark consisted of building a clang 8.0 binary configured with:

  -DCMAKE_BUILD_TYPE=RelWithDebInfo \
  -DLLVM_TARGETS_TO_BUILD=X86 \
  -DLLVM_USE_SANITIZER=Address \
  -DCMAKE_CXX_FLAGS="-Xclang -femit-debug-entry-values -stdlib=libc++"

The average wall clock time increased by 4 seconds, from 62:05 to
62:09, which is an 0.1% increase.

Reviewers: aprantl, vsk, djtodoro, NikolaPrica

Reviewed By: vsk

Subscribers: hiraditya, ychen, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D67261
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The file was modified/llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h (diff)llvm.src/include/llvm/CodeGen/TargetInstrInfo.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (diff)llvm.src/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was modified/llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp (diff)llvm.src/lib/CodeGen/TargetInstrInfo.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (diff)llvm.src/lib/Target/X86/X86InstrInfo.cpp