Started 4 mo 2 days ago
Took 1 hr 1 min on green-dragon-09

Success Build #6532 (Feb 22, 2019 11:59:30 AM)

  • : 354688
  • : 354537
  1. MIR: Preserve incoming frame index numbers

    Don't skip incrementing the frame index number
    if the object is dead. Instructions can still be
    referencing the old frame index number, and this
    doesn't attempt to remap those. The resulting
    MIR then fails to load because the use instructions
    use a higher frame index number than recorded
    list of stack objects.

    I'm not sure it's possible to craft a testcase
    with the existing set of passes. It requires
    selectively marking some stack objects
    dead in an essentially random order.
    StackSlotColoring condenses towards
    the low indexes. This avoids a regression in a
    future AMDGPU commit when some frame indexes
    are lowered separately from PEI. (detail)
    by arsenm
  2. CodeGen: Make RegAllocRegistry a template class

    Will allow re-using the machinery for independent
    sets of register allocators.

    This will allow AMDGPU to use separate command line
    options for the allocator to use for SGPRs separate
    from VGPRs. (detail)
    by arsenm
  3. AMDGPU: Use removeAllRegUnitsForPhysReg (detail)
    by arsenm
  4. LiveIntervals: Add removeAllRegUnitsForPhysReg

    Convenience wrapper for removing the reg units of
    a physical register. (detail)
    by arsenm
  5. [WebAssembly] Remove debug statement submitted in rL354657

    Subscribers: dschuff, jgravelle-google, hiraditya, aheejin, sunfish, llvm-commits

    Tags: #llvm

    Differential Revision: (detail)
    by sbc
  6. [GN] Updated build file to allow GN builds to succeed at ToT. (detail)
    by hctim
  7. [MBP] Factor out function hasViableTopFallthrough and enhancement

    This patch factor out the function hasViableTopFallthrough from rotateLoop. It is also enhanced. Original code checks only if there is a block can be placed before current loop top. This patch also checks if the loop top is the most possible successor of its predecessor. The attached test case shows its effect.

    Differential Revision: (detail)
    by carrot
  8. Disable big-endian constant store merges from rL354676. (detail)
    by niravd

Started by an SCM change (7 times)

This run spent:

  • 3 hr 35 min waiting;
  • 1 hr 1 min build duration;
  • 4 hr 37 min total from scheduled to completion.
Test Result (no failures)