Started 4 mo 2 days ago
Took 1 hr 1 min on green-dragon-09

Success Build #5366 (Feb 22, 2019 1:00:57 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 354692
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 354537
Changes
  1. Restore ability for C++ API users to Enable IPRA.

    Summary:
    Prior to r310876 one of our out-of-tree targets was enabling IPRA by modifying
    the TargetOptions::EnableIPRA. This no longer works on current trunk since the
    useIPRA() hook overrides any values that are set in advance. This patch adjusts
    the behaviour of the hook so that API users and useIPRA() can both enable it
    but useIPRA() cannot disable it if the API user already enabled it.

    Reviewers: arsenm

    Reviewed By: arsenm

    Subscribers: wdng, mgorny, llvm-commits

    Differential Revision: https://reviews.llvm.org/D38043 (detail)
    by dsanders
  2. [CGP] move overflow intrinsic insertion to common location; NFCI

    We need to enhance the uaddo matching to handle special-cases
    as seen in PR40486 and PR31754. That means we won't necessarily
    have a def-use pattern, so we'll need to check dominance to
    determine where to place the intrinsic (as we already do for
    usubo). This preliminary patch is just rearranging the code,
    so the planned follow-up to improve uaddo will be more clear. (detail)
    by spatel
  3. MIR: Preserve incoming frame index numbers

    Don't skip incrementing the frame index number
    if the object is dead. Instructions can still be
    referencing the old frame index number, and this
    doesn't attempt to remap those. The resulting
    MIR then fails to load because the use instructions
    use a higher frame index number than recorded
    list of stack objects.

    I'm not sure it's possible to craft a testcase
    with the existing set of passes. It requires
    selectively marking some stack objects
    dead in an essentially random order.
    StackSlotColoring condenses towards
    the low indexes. This avoids a regression in a
    future AMDGPU commit when some frame indexes
    are lowered separately from PEI. (detail)
    by arsenm
  4. CodeGen: Make RegAllocRegistry a template class

    Will allow re-using the machinery for independent
    sets of register allocators.

    This will allow AMDGPU to use separate command line
    options for the allocator to use for SGPRs separate
    from VGPRs. (detail)
    by arsenm
  5. AMDGPU: Use removeAllRegUnitsForPhysReg (detail)
    by arsenm
  6. LiveIntervals: Add removeAllRegUnitsForPhysReg

    Convenience wrapper for removing the reg units of
    a physical register. (detail)
    by arsenm
  7. [WebAssembly] Remove debug statement submitted in rL354657

    Subscribers: dschuff, jgravelle-google, hiraditya, aheejin, sunfish, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D58549 (detail)
    by sbc

Started by an SCM change (3 times)

This run spent:

  • 2 hr 0 min waiting;
  • 1 hr 1 min build duration;
  • 3 hr 1 min total from scheduled to completion.
Test Result (no failures)